United Microelectronics Corp.

Ching-Chiao Hao

Kun-Chi Lin

Kevin Lin

Hua-Chou Tseng

Chih-Yuan Hsiao

A method for forming a gate contact is disclosed. The method includes that a semiconductor substrate and a silicon dioxide layer are provided upon the semiconductor substrate. Then, a polysilicon layer is formed upon the oxide layer. Next, defining and etching the polysilicon layer are carried out to form a gate. Implanting upon the top surface of the silicon dioxide layer is achieved so that source/drain region is formed below and abuts the silicon dioxide layer. The source/drain region will be annealed. A spacer can be formed and abuts the sidewall of the gate. A salicide is formed and overlaps the top surface of the gate and over the semiconductor substrate. Then, a gate contact area can be defined upon the top surface of the semiconductor substrate by using a mask that has a pattern covering approximately half of the gate and the spacer. The half of the spacer can be removed without covering by the mask. Finally, implanting will be completed to form the gate contact in the substrate by using the salicide as an implanting mask.

Method for forming gate contact in complementary metal oxide semiconductor

A method for fabricating a type of bit line is able to form a small-sized bit line. In this method a first dielectric layer, a first conductive layer, and a second conductive layer are formed on a substrate in sequence. The first dielectric layer is exposed, then a second conducting wire and a first conducting wire are formed, respectively. A portion of the second conducting wire is removed by a cleaning liquid, so that the feature size of the second conducting wire is less than the feature size of the first conducting wire. An oxide layer is formed on the second conducting wire and the first conducting wire by performing a thermal treatment. The feature size of the second conducting wire is approximately equal to the feature size of the first conducting wire.

Simple small feature size bit line formation in DRAM with RTO oxidation

A method of forming small dimension wires by an isotropic removal process. The method provides a substrate with an insulation layer. A first conductive layer and a second conductive layer are formed on the insulation layer. A wire pattern is formed on a photoresist layer after the coating process and the sequential exposure and development process. Part of the second conductive layer is removed by using the wire pattern on the photoresist layer as a mask, and thus part of the second conductive layer with wires is remained. Isotropic etching the peripheral part of the second conductive layer and thus the part of wire pattern with a smaller dimension is remained. Using the wire pattern with a smaller dimension as a mask to anisotropic etch the first conductive layer until the surface of the insulation layer is exposed, and thus the process of fabricating small dimension is finished.

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Hsinchu, Taiwan

Ching-Chiao Hao