United Microelectronics Corp.

Ching-Cheng Lung

Yu-Tse Kuo

Chun-Hsien Huang

Chun-Yen Tseng

Shu-Ru Wang

Li-Ping Huang

Hsin-Chih Yu

Chien-Hung Zordius Chen

Chih-Wei Tsai

Meng-Ping Chuang

Shih-Hao Liang

Koji Nii

Yuichiro Ishii

Hung-Chan Lin

Shao-Hui Wu

Chang-Hung Chen

Wei-Chi Lee

Tien-Yu Lu

Ting-Hao Chang

Shou-Sian Chen

Ting-Chia Chang

A layout pattern of a two-port ternary content addressable memory (TCAM) includes a first storage unit, a second storage unit, a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit are positioned in a first side area of a side and a second side area of another side of the layout pattern, respectively. The first storage unit and the second storage unit are positioned in a first middle area and a second middle area between the first side area and the second side area, respectively. The first storage unit is connected to the first comparison circuit through a first gate structure and connected to the second comparison circuit through a second gate structure. The second storage unit is connected to the first comparison circuit through a third gate structure and connected to the second comparison circuit through a fourth gate structure.

Layout pattern of two-port ternary content addressable memory

A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.

Two-port ternary content addressable memory and layout pattern thereof, and associated memory device

A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.

Ternary content addressable memory unit capable of reducing charge sharing effect

A layout pattern of a static random access memory (SRAM) preferably includes a first inverter and a second inverter. Preferably, the first inverter includes a first gate structure extending along a first direction on a substrate, in which the first gate structure includes a gate of a first pull-up device (PL) and a gate of a first pull-down device (PD). The second inverter includes a second gate structure extending along the first direction on the substrate, in which the second gate structure includes a gate of a second pull-up device (PL) and a gate of a second pull-down device (PD) and the gate of the PDis directly under the gate of the PD

Layout pattern of a static random access memory

A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.

Static random access memory

A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL), a first pull-down transistor (PD), a second (PL), and a second pull-down transistor (PD) on the substrate, and a first pass gate transistor (PGA), a second pass gate transistor (PGB), a third pass gate transistor (PGA) and a fourth pass gate transistor (PGB), wherein the PGA and the PGB comprise a first fin structure, the PGA and the PGB comprise a second fin structure, a first local interconnection layer disposed between the PGA and the PGB and disposed on the fin structures of the PLand the PD, a second local interconnection layer disposed between the PGA and the PGB and disposed between the fin structures of the PLand the PD, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

Static random access memory structure

A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.

Semiconductor device and semiconductor apparatus

The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.

Memory device with oxide semiconductor static random access memory and method for operating the same

A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.

Dual port static random access memory (DPSRAM) cell

A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.

Control circuit used for ternary content-addressable memory with two logic units

A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL), a first pull-down transistor (PD), a second (PL), and a second pull-down transistor (PD) on the substrate, and a first pass gate transistor (PGA), a second pass gate transistor (PGB), a third pass gate transistor (PGA) and a fourth pass gate transistor (PGB), wherein the PGA and the PGB comprise an identical first fin structure, the PGA and the PGB comprise an identical second fin structure, a first local interconnection layer disposed between the PGA and the PGB and disposed on the fin structures of the PLand the PD, a second local interconnection layer disposed between the PGA and the PGB and disposed between the fin structures of the PLand the PD

Layout pattern for static random access memory

The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL) and a first pull-down transistor (PD), a second inverter comprises a second pull-up transistor (PL) and a second pull-down transistor (PD), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD, the PD, the SW, and the PG comprise a first diffusion region, the PLand the PLcomprise a second diffusion region.

Layout pattern of a memory device formed by static random access memory

The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

Static random-access memory device

The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.

Six-transistor static random access memory cell and operation method thereof

The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.

Growing community of inventors

Tainan, Taiwan

Ching-Cheng Lung