Hirose Electric Company, Ltd.

Optimal, Inc.

Ataitec Corporation

Rambus Inc.

Hirose Electric

Ching-Chao Huang

Jeremy Buan

Tadashi Ohshida

Clement Kam Lam Luk

Tatsuya Arai

Jingqian Tian

Frank Lambrecht

Toshiyuki Takada

Tsutomu Matsuo

Nobuhiro Tamai

Masakazu Nagata

Shota Yamada

Kunia Aihara

Gong-Jong Yeh

Clement Luk

Michael Fox

Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.

Systems and methods to reduce differential-to-differential far end crosstalk

A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.

The present disclosure involves method and apparatus for de-embedding test fixture to extract the electrical behavior of device under test. A calibration board with both '1&#xd7; open' and '1&#xd7; short' test structures is fabricated and measured by equipment such as vector network analyzer that produces S parameters. The S parameters of &#x201c;1&#xd7; open&#x201d; and &#x201c;1&#xd7; short&#x201d;, with or without correction factors, are combined to produce the S parameters of equivalent &#x201c;2&#xd7; thru&#x201d; test structure. The S parameters of equivalent &#x201c;2&#xd7; thru&#x201d; are used subsequently to de-embed the test fixture. This present disclosure gives a simpler and more accurate method to create the S parameters of &#x201c;2&#xd7; thru&#x201d; for de-embedding.

Fixture de-embedding using calibration structures with open and short terminations

The first terminals have contact arm portions extending in a rectilinear manner in the direction of connector plugging and unplugging; the second terminals have convex contact point portions contactable with an intermediate portion of the contact arm portions in the same direction. When the stub portions of the contact arm portions are divided into a free end side range and a proximal end side range such that the center point of said stub portions in the direction of plugging and unplugging forms a boundary, in the arranged state of the first terminals, impedance at arbitrary locations in the direction of plugging and unplugging within the free end side range is larger than impedance at arbitrary locations in the plugging direction within the proximal end side range.

Electrical connector assembly and electrical connector for use in same

Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.

Mitigation of connector stub resonance

Systems, methods and apparatuses involving a chip-to-chip communication channel, for reducing Far End Crosstalk (FEXT) through the novel concept of controlling FEXT magnitude and polarity of a component inside a channel, vias or within a connector by implementing broadside and edge couplings to offset cumulative FEXT in a channel, via-connector-via subsystem or a connector. The example implementations described herein can be applied to a chip-to-chip communication channel, mezzanine connectors, backplane connectors and any other connectors requiring via routing, and connector itself that can benefit from FEXT reduction.

Method and apparatus for reducing far-end crosstalk in electrical connectors

The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.

Reducing far-end crosstalk in electrical connectors

A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.

Resonant frequency shifted connector

An RLGC library is generated so as to include fringe RLCG functions for 2-D canonical interconnect structures. During parameter extraction for selected interconnect structures of an integrated circuit, printed circuit board, or integrated circuit package design, the RLGC library is used to generate fringe RLGC coefficients which in addition to area RLGC coefficients calculated on-the-fly, are used to generate equivalent RLGC circuits or S-parameters for simulating the interconnect structures.

Fringe RLGC model for interconnect parasitic extraction

A method for modeling a triangle meshed interconnect structure using an electrically equivalent three rectangle combination for each triangle in the triangle mesh is described. In the method, a surface of an interconnect structure is meshed with triangles. Three rectangles are then defined for each triangle so that each rectangle shares a different side of the triangle. Rectangle circuit models are determined so that the three rectangles are approximately equivalent electrically to the triangle when coupled together. The interconnect circuit model is then formed by connecting together the rectangle circuit models for all triangles defined on the surface of the interconnect structure.

Method for modeling triangle meshed interconnect structures using an electrically equivalent three rectangle combination for each triangle in the triangle mesh

A technique for determining performance characteristics of electronic systems is disclosed. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.

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San Jose, CA, United States of America

Ching-Chao Huang