Samsung Electronics Co., Ltd.

Chinam Kim

Dohan Kim

Insu Choi

Changmin Lee

Tae-Kyeong Ko

Namhyung Kim

Cholmin Kim

Byeongnoh Kim

Bobae Kim

Kyeongjin Cho

Taekyeong Ko

A semiconductor memory system includes a memory device including plural banks, and a memory controller that generates an offset address for a first bank among the plural banks and a command indicating the offset address, based on a first request. The memory device generates a first address by adding the offset address to a base address for the first bank, according to the command, and performs a memory operation on the first address of the first bank according to the command.

Address decoding method, and memory controller and semiconductor memory system using the same

A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

Memory device including address table and operating method for memory controller

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SUWON-SI, South Korea

Chinam Kim