Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Yuan Ko

Hsi-Yu Kuo

Yu-Lin Chu

Ming-Yih Wang

Pei-Chun Liao

Yao-Jen Tsai

Te-Liang Lee

Chia-Lin Chen

Chih-Fu Chang

Yung-Sheng Tsai

Sheng Chiang Hung

Sheng-Hui Liang

Keng-Hui Liao

Chih-kai Yang

Chih-fu Chang

Chia-Jen Leu

An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first intermetal dielectric (IMD) layer disposed over a plurality of conductive features and a first passive component disposed on the first IMD layer in a first region of the substrate. The structure further includes a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.

Interconnect structure and methods of forming the same

A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.

Semiconductor structure including discharge structures and method for fabricating the same

An integrated circuit (IC) structure is provided. The IC structure comprises a deep n-well (DWN), a first circuit, a second circuit, a first power line and a second power line. The first circuit is in the DWN. The second circuit is outside the DWN and electrically connected with the first circuit. The first power line is configured to provide the first circuit with power. The second power line is configured to provide the second circuit with power. The second power line is electrically connected with the first power line. The first power line and the second power line are in different conductive layers.

Semiconductor device and method of manufacturing the same

An electronic device is disclosed that includes an output device and a detection circuit. The output device is coupled to an output pad, and is turned on according to a protection signal. The detection circuit is configured to detect a voltage level of a control node, to generate the protection signal based on the detected voltage level, and to switch the voltage level to a predetermined voltage level according to the detected voltage level.

Protection circuit for output device

A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.

Two-transistor non-volatile memory cell and related program and read methods

A circuit that includes a first diode-connected dummy device, a second diode-connected dummy device, a third diode-connected dummy device, a fourth diode-connected dummy device, and a first discharge path. The second diode-connected dummy device connected in cascode with the first diode-connected dummy device. The fourth diode-connected dummy device connected in cascode with the third diode-connected dummy device. The first and the second diode-connected dummy devices are formed in a first region. The third and the fourth diode-connected dummy devices are formed in a second region which is outside the first region. The first discharge path configured to discharge charges from at least one of the first and the second diode-connected dummy devices in the first region to a reference voltage terminal of one of the third and the fourth diode-connected dummy devices in the second region.

Protection circuit

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region.

Semiconductor device and method of manufacturing a semiconductor device

A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.

Method for testing semiconductor devices

An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder.

Growing community of inventors

Hsinchu, Taiwan

Chin-Yuan Ko