Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Yu Mei

Wen-Ting Chu

Yu-Wen Liao

Po-Hao Tseng

Yong-Shiuan Tsair

Chieh-Fei Chiu

A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Memory device having two memory stacks over one bottom electrode

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.

Memory structure

Method for manufacturing memory device having spacer

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.

Growing community of inventors

Hsinchu, Taiwan

Chin-Yu Mei