Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Yi Cho

Jung-Huei Peng

Yao-Te Huang

Li-Min Hung

Chun-Wen Cheng

Chia-Hua Chu

Shang-Ying Tsai

Yi-Chuan Teng

Hsin-Ting Huang

Lin-Min Hung

The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

Structure for integrated microphone

An embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

Method for manufacturing a microphone

A wafer seal ring may be formed on a wafer having a pattern structure with a pattern density. The wafer seal ring pattern structure may include a plurality of lines having a width and a spacing that may be approximately equal to a width and a spacing of die bond rings on the wafer. The wafer having the wafer seal ring formed thereon may be bonded to a wafer that may not have a wafer seal ring. A pair of wafers may be formed with respective wafer seal rings formed in a corresponding manner. The pair of wafers may be bonded together with the wafer seal rings aligned and bonded together to form a seal ring structure between the bonded wafers.

Method and apparatus for a wafer seal ring

According to an exemplary embodiment of the disclosure, a method of removing a waste part of a substrate is provided. The method includes: using a laser to partially drill the substrate to define the waste part; and applying megasonic vibration to the substrate to remove the waste part from the substrate.

Method of removing waste of substrate and waste removing device thereof

Some embodiments relate to a manufacturing process that combines a MEMS capacitor of a microelectromechanical systems (MEMS) microphone and an integrated circuit (IC) onto a single substrate. A dielectric is formed over a device substrate. A conductive diaphragm and a conductive backplate are formed within the dielectric, with a sacrificial portion of the dielectric between them. A first recess is formed, which extends through the dielectric to an upper surface of the conductive diaphragm. A second recess is formed, which extends through the substrate and dielectric to a lower surface of the conductive backplate. The sacrificial layer is removed to create an air gap between the conductive diaphragm and the conductive backplate. The air gap joins the first and second recesses to form a cavity that extends continuously through the dielectric and the substrate. The present disclosure is also directed to the semiconductor structure of the MEMS microphone resulting from the manufacturing process.

Monolithic complementary metal-oxide semiconductor (CMOS)-integrated silicon microphone

In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

Wafer level packaging techniques

The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate; a silicon oxide layer formed on one side of the first silicon substrate; a second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates; and a diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates, wherein the first plate and the diaphragm are configured to form a capacitive microphone.

Structure and method for integrated microphone

A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.

Systems and methods for post-bonding wafer edge seal

A structure comprises a first semiconductor substrate, a first bonding layer deposited on a bonding side the first semiconductor substrate, a second semiconductor substrate stacked on top of the first semiconductor substrate and a second bonding layer deposited on a bonding side of the second semiconductor substrate, wherein the first bonding layer is of a horizontal length greater than a horizontal length of the second semiconductor substrate, and wherein there is a gap between an edge of the second bonding layer and a corresponding edge of the second semiconductor substrate.

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Kaohsiung, Taiwan

Chin-Yi Cho