Via Technologies, Inc.

Via Technology, Inc.

Chin-Yi Chiang

Wallace Huang

Chun-Hua Tseng

Yu-Wei Chang

Tse-Hsien Wang

Chin-Fa Hsiao

Ching-Chung Lai

Tung-Chih Kuo

Jeffrey Kuo

Abel Lien

Chien-Zhi Chen

Giga Hsu

An image frame transmission method for use in a network transmission system is provided. The network transmission system includes an image sensor and an image processor. Firstly, a first image data segment of an image frame captured by the image sensor is outputted to the image processor in response to a first state of a control signal after an initial signal has been asserted by the image processor. Then, the output of a second image data segment of the image frame following the first image data segment to the image processor is delayed in response to the transition of the control signal from the first state to a second state. Afterward, the second image data segment is outputted to the image processor in response to the transition of the control signal from the second state to the first second state.

Image frame transmission method for data overrun control

In a method for sampling image data from an image frame with component video, the image frame includes a first component frame, a second component frame and a third component frame. The method comprises steps of selecting a first component portion, a second component portion and a third component portion from the first component frame, the second component frame and the third component frame, respectively; and operating the first component portion, the second component portion and the third component portion to obtain a sampled unit arranged as a block array. The sampled unit includes at least a first component blocks derived from the first component portion, a second component block derived from the second component portion and a third component block derived from the third component portion.

Image data sampling method

In an image-frame processing method, the image frame is outputted from and image sensor by an image processor via the buffering of a memory buffer. The method includes the following steps of: defining at least two storage spaces in the memory buffer; dividing the image frame into a plurality of image portions, each of which has a size corresponding to the size of one of said at least two storage spaces; sequentially storing the image portions into the storage spaces in turn; and sequentially processing said image portions stored in the memory buffer. This method is applicable to processing the image frame with the use of a small-sized memory buffer.

Method for processing image frame output from an image sensor by an image processor

A method and an apparatus for image compression. First, an image is partitioned into a plurality of image blocks, the image having A&#xd7;B pixels, each of the image blocks having N&#xd7;M pixels, wherein N is less than A and M is less than B. Next, a selected image block is outputted by selecting one of the image blocks as the selected image block. After that, a compressed image block is produced by storing the selected image block and compressing the selected image block. The step of outputting the selected image block and the step of producing the compressed image block are repeated until the image blocks are compressed into a plurality of compressed image blocks. Finally, a compressed image file is produced according to the compressed image blocks.

Method and apparatus for image compression

A memory card and a control chip capable of supporting various voltage supplies and a method of supporting voltages are discussed. The memory card includes a flash memory and a control chip for controlling the flash memory, and the control chip has a voltage regulator, a pad power supplier, a core controller and an output circuit. The voltage regulator transforms an external working voltage into a working voltage. The pad power supplier receives the external working voltage and adjusts a level of the external working voltage to output a pad working voltage according to an operating mode. The core controller receives the working voltage to work and generates a control signal. The output circuit receives the control signal and outputs a memory control signal according to a level of the pad working voltage. The control chip controls a flash memory with the memory control signal.

Memory card and control chip capable of supporting various voltage supplies and method of supporting voltages thereof

An accessing apparatus capable of reducing power consumption and an accessing method thereof are provided. The accessing method is applied in the accessing apparatus and a host. Firstly, the accessing apparatus is enabled to transmit an external data with the host according to an external clock, and transmit an internal data corresponding to the external data inside the accessing apparatus according to an internal clock. Next, the frequency of the external clock is detected. Then, the frequency of the internal clock is adjusted to a corresponding frequency according to the frequency of the external clock. Lastly, the internal data is transmitted between a buffer and a memory unit of the accessing apparatus by using an internal clock whose frequency equals the corresponding frequency.

Accessing apparatus capable of reducing power consumption and accessing method thereof

The disclosure relates to a data arranging method of a flash memory for improving access performance. The method includes steps of storing a first data sector to a page of the flash memory; storing a first data correction set corresponding to the first data sector in the page of the flash memory, wherein the first data correction set is next and contiguous to the first data sector; and repeating the two storing steps for storing a plurality of data sectors and a plurality of corresponding data correction sets until the page is formed.

Data arrangement and data arranging method in storage device

The invention is applied in a gigabit network environment. During the process of converting serial data into parallel data, a method is proposed to use the comma pattern in a data pipeline architecture to select word boundaries of a correct data frame from a serial bit stream. This method is further implemented in a bit receiver with a two-stage pipeline architecture to achieve the object of increasing data transmission bandwidth and efficiency.

Device and method for comma detection and word alignment in serial transmission

A circuit module of a memory card is selectively used with card readers/writers compliant with different access protocols. The circuit module includes a shared non-volatile memory; a first transmission control unit communicable with a first card reader/writer for controlling data transmission from/to the first card reader/writer; a second transmission control unit communicable with a second card reader/writer for controlling data transmission from/to the second card reader/writer; and a data buffer and memory access controller coupled to the non-volatile memory and the first and second transmission control units for conducting a data transmission path between a designated transmission control unit and the non-volatile memory, thereby allowing data transmission between the designated card reader/writer and the non-volatile memory. The circuit module can be grouped with different carrier housings to produce a memory card kit.

Circuit module and memory card kit compliant with various access protocols

A method for driving a flash memory and flash memory apparatus thereof are provided. The flash memory apparatus comprises a flash memory controller and a flash memory. At first, a voltage level of the parameter definition pin is detected by the flash memory controller to obtain the basic configuration of the flash memory when the flash memory controller is in a reset mode. Next, a fundamental access operation is performed on the flash memory by the flash memory controller according to the basic configuration. Then, a detail configuration is read from a specific data block of the flash memory. At last, the flash memory is driven according to the basic configuration and the detail configuration of the flash memory.

Method and apparatus for driving flash memory

A chip capable of performing self testing includes: an output circuit for generating output signals; a transmitting circuit coupled to the output circuit for transmitting output signals generated by the output circuit; a receiving circuit for receiving signals transmitted to the chip and generating corresponding receiving signals; a first multiplexer; and an input circuit coupled to an output port of the first multiplexer for receiving outputs of the first multiplexer, wherein the first multiplexer includes: a first input port coupled to the output circuit for receiving output signals generated by the output circuit; and a second input port coupled to the receiving circuit for receiving signals generated by the receiving circuit.

Method and related apparatus for chip testing

A Circuit for reducing the number of serial ATA external PHY signals includes: a serializer/deserializer, connected to a storage medium controller through a set of parallel signal transmitting lines and a set of parallel signal receiving lines, so as to convert signals between parallel and serial specifications; a phase locked loop, connected to the serializer/deserializer so as to generate a clock signal required for data signal transmission; at least one pair of transmitter and receiver, each connected to the serializer/deserializer, each transmitter able to transmit the serial data signal from the serializer through a set of serial signal transmitting lines to a serial ATA device, and each receiver able to receive the serial data from the serial ATA device through a set of serial signal receiving lines to the deserializer; and at least one OOB signal detector, each connected to the corresponding receiving lines, so as to detect the out of band signals from the serial ATA device. The Circuit also employs in certain applications a signal encoding approach for reducing the number of serial ATA external PHY signals, wherein an encoder and a decoder are employed to encode control signals and status signals into special data codes transmitted between a serial ATA external PHY and a storage medium controller, so as to minimize the number of interface signals.

Circuit and signal encoding method for reducing the number of serial ATA external PHY signals

The present invention discloses a universal serial bus (USB) control circuit, and more particularly, a USB control circuit with an automatic route-switching function. The USB control circuit comprises: a plurality of USB pads, connecting a plurality of USB devices; a plurality of USB transceivers, each connected to a corresponding USB pad; at least one USB controller, each connected to at least one corresponding USB transceivers, so as to control and drive the USB devices connected to the corresponding USB pads by using the corresponding USB transceivers; a plurality of port routing controllers, each connected to a corresponding USB transceiver; at least one enhanced USB transceivers, each connected to each of the USB pads and each of the port routing controllers; an enhanced USB controller, connected to each of the enhanced USB transceivers, so as to control and drive the enhanced USB devices connected to the corresponding USB pads by using the corresponding enhanced USB transceivers; and an enhanced device routing controller, connected to each of the port routing controllers, so as to automatically switch a USB pad that connects enhanced USB devices to the enhanced USB transceivers to be controlled by the enhanced USB controller.

USB control circuit with automatic route-switching function

The present invention improves the drawback of requiring more clock signals in conventional high-frequency serial-to-parallel conversions that often use multi-phase clock circuits. The needed number of phase clocks is the bit width of the parallel data. In addition to effectively reduce the number of required clocks, the present invention can further solve the setup time problem associated with the switching one of two parallel data receivers as the parallel data output. A pre-register is employed in the converter of the present invention. Since this pre-register does not need switch control, it does not have the setup time problem during parallel data switching.

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Taipei, Taiwan

Chin-Yi Chiang