Advanced Micro Devices Corporation

Globalfoundries Inc.

Chin-Wei Kate Liang

Chi-Sheng Chang

Robert Alan Williams

Jeffrey Roy Dwork

Kevin Pond, Legal Representative

Matthew James Fischer

Somnath Viswanath

Marufa Kaniz

Hung Duy Vo

Tsai-Lung Lee

A network interface system includes a memory system for managing data obtained via a system bus that supports split transactions. The memory system comprises a first memory for storing outgoing assembled data frames and associated control information prior to transfer of the outgoing data to the network, and an assembly memory that stores unassembled outgoing data from the bus. A memory control system stores the control information associated with pending bus read requests and also transfers outgoing data from the assembly memory to the first memory when all the outgoing data for a corresponding read request has been assembled.

Network interface with secondary data and packet information storage and memory control systems to accommodate out-of-order data processing and split transactions on a host system bus

Network interface systems are disclosed comprising a bus interface system, a media access control system, a memory system, a security system for selectively encrypting outgoing data and decrypting incoming data, a checksum system for generating and verifying checksum values, and a segmentation system for selectively segmenting outgoing data, where the network interface system may be fabricated as a single integrated circuit chip. Methods are also provided for interfacing a host system with a network, in which checksum information is obtained from the host system, which is used to generate checksum values for outgoing data while the data is being stored in a network interface memory system.

Network interface systems and methods for offloading segmentation and/or checksumming with security processing

One aspect of the invention relates to a network interface system for interfacing a host system with a network. The network interface system includes a bus interface system, a media access control system, a memory system, and a security system. The media access control system comprises one or more local buffers and is adapted to read a second data frame from the memory system while a first data frame is being transmitted to the network. The invention is particularly useful when the memory system has a single memory sharing several clients. When a memory has several clients, there can be instances where a read of the memory by the media access control system is delayed because the memory is busy with a request from another client. The invention helps ensure that such delays do not result in transmission errors and reduces the effect of such delays on overall transmission speed.

Prefetch scheme to minimize interpacket gap

A networking interface device for coupling a system host having one of a plurality configurations to a network medium. The device having a peripheral component interconnect (PCI) interface for coupling the interface device to a system host configured with a PCI based system bus interface; a medium independent interface (MII) for coupling the interface device to a system host configured with a media access controller (MAC) based system bus interface; and a control block for determining whether the interface device is operably coupled to a system host having a PCI based system bus interface or a MAC based system bus interface.

PCI and MII compatible home phoneline networking alliance (HPNA) interface device

A network node has multiple physical layer devices (PHYs), multiple media access controllers, and means for gathering and utilizing information regarding the capabilities of other nodes on the network. The node capability information may be gathered using hardware or software, and may involve gathering information from data frames received by the node, and/or from capability and status announcement frames received by the node. Hardware means for gathering the node capability information may include a receive processing block and/or a node discovery block, which examine all or portions of received frames, and which include a look-up table for storing and receiving information such as desired transmission rates for frames sent to other nodes. The PHYs of the interface in an exemplary embodiment are able to transmit and receive data frames or packets which are in accordance with different home phoneline networking alliance (HPNA) specifications, for example, HPNA 1.0 and HPNA 2.0.

Method to select transmission rate for network device

A networking interface device for coupling a system host having one of a plurality configurations to a network medium. The networking device has a peripheral component interconnect (PCI) interface for coupling the interface device to a system host configured with a PCI based system bus interface; a medium independent interface (MII) for coupling the interface device to a system host configured with a media access controller (MAC) based system bus interface; a PCI control block for managing network data packet traffic exchange between the interface device and the system host; and an MII attachment coupled between the MII and the PCI control block, the MII attachment reformatting management data packets such that the MAC based system bus interface appears to be a PCI based system bus interface by the PCI control block.

A networking interface device for coupling a system host having one of a plurality configurations to a network medium. The networking interface device has a peripheral component interconnect (PCI) interface for coupling the interface device to a system host configured with a PCI based system bus interface; a medium independent interface (MII) for coupling the interface device to a system host configured with a media access controller (MAC) based system bus interface; and a buffer management device (BMU) having an active state for bursting data packet traffic via the PCI interface when the interface device is coupled to a PCI based system bus interface and a passive state for continuously passing data packet traffic via the MII when the interface device is coupled to a MAC based system bus interface.

A network switch having on-board MIB counters employs a random access memory to store statistics counters (MIB counters). The random access memory is a multiple port memory at which simultaneous read and write access operations may be performed. A pipeline is coupled to this memory to control the read and write accesses and prevent a simultaneous reading and writing of the same MIB counter at the same address in the memory.

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Sunnyvale, CA, United States of America

Chin-Wei Kate Liang