Chunghwa Picture Tubes, Ltd.

Chungwha Picture Tubes, Ltd.

Chunghua Picture Tubes, Ltd.

Chin-Tzu Kao

Ya-Ju Lu

Wen-Cheng Lu

Ta-Jung Su

Yi-Tsai Hsu

Hsiang-Hsien Chung

Ying-Ming Wu

Yu-Tsung Lee

Kuo-Wei Wu

Chi-Ming Chiou

Jin-Chuan Kuo

Jui-chung Chang

Pei-Nong Lu

Fu-Liang Lin

Yung-Hsin Wu

Chien-Pang Tai

Chung-Hsu Wang

Chia-Che Hsu

Wei-Hsin Lee

Da-Yo Liu

Jui-Chung Chang

A method for fabricating a planarization layer includes: forming an active device on a substrate; covering the active device with a passivation layer; forming a pad layer on the passivation layer; forming an overcoating layer covering the passivation layer and the pad layer on the substrate; and removing a portion of the overcoating layer and the pad layer by an exposure and development process to form a patterned overcoating layer, wherein the patterned overcoating layer has an opening exposing the passivation layer on a position relative to the active device. The method for fabricating the planarization layer of the disclosure may save exposure to enhance productivity.

Method for fabricating planarization layer

The invention provides a forming method of a via hole, including: sequentially stacking a patterned first conductive layer, a first insulating layer, a patterned second conductive layer, and a second insulating layer on a substrate. The second conductive layer and the first conductive layer overlap in a normal direction of the substrate, such that the second insulating layer has a protrusion portion protruding away from the substrate. A photosensitive material layer covers the second insulating layer. The photosensitive material layer is exposed, wherein a depth of exposure is equal to a vertical distance from a top surface of the protrusion portion to a surface of the photosensitive material layer. The exposed photosensitive material layer is removed by development to form a first via hole exposing the second insulating layer. The exposed second insulating layer is etched to form a second via hole to expose the second conductive layer, and then the photosensitive material layer is removed. A manufacturing method of a pixel structure, using the forming method of the via hole, is also provided.

Forming method of via hole and manufacturing method of pixel structure

The invention relates to a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor includes the following steps: an insulating layer is formed to cover a gate on a substrate; a semiconductor pattern having a first region and a second region is formed on the insulating layer; a plurality of island patterns is formed, wherein at least a portion of the plurality of island patterns is disposed on the semiconductor pattern, and the plurality of island patterns is separated from one another by a gap; and a source and a drain are formed to cover a portion of the plurality of island patterns and fill the gaps to respectively be electrically connected to the first region and the second region of the semiconductor pattern.

Thin-film transistor and manufacturing method thereof

A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.

TFT with oxide layer on IGZO semiconductor active layer

A manufacturing method of a thin film transistor includes the following steps. A substrate is provided first. A semiconductor layer is then formed on the substrate. Next, a photoresist pattern including a middle portion and two peripheral portions is formed on the semiconductor layer. The middle portion is disposed between two peripheral portions, and the thickness of the middle portion is greater than each of the peripheral portions. Next, an etching process is performed on the semiconductor layer for forming a patterned semiconductor layer. A photoresist ashing process is then performed to remove at least the peripheral portions of the photoresist pattern to form a channel defining photoresist pattern and expose two portions of the patterned semiconductor layer. Next, the patterned semiconductor layer is treated to form a semiconductor portion and two conductor portions. The channel defining photoresist pattern is then removed.

Thin film transistor and manufacturing method thereof

Oxidizing the source and doping the drain of a thin-film transistor

A TFT substrate includes: a substrate; and a plurality of TFTs, wherein each of the TFTs comprises: a gate electrode, disposed on the substrate; a gate insulating layer, disposed on the substrate and covering the gate electrode; a metallic oxide active layer, disposed on the gate insulating layer; a metallic oxide protection layer, disposed on the metallic oxide active layer; an etching stop layer, disposed on the metallic oxide protection layer, wherein a first through hole and a second through hole penetrate through the etching stop layer and the metallic oxide protection layer; and a source electrode and a drain electrode, disposed in the first through hole and the second through hole respectively, and electrically connected to the metallic oxide active layer.

Thin film transistor substrate

The present invention provides a pixel structure including a substrate, a first metal pattern layer, an insulating layer, a second metal pattern layer, a passivation layer, and a conductive protection layer. The substrate has at least one pixel region. The first patterned metal layer is disposed on the substrate, and has a top surface. The insulating layer is disposed on the first patterned metal layer and the substrate, and is in contact with the top surface of the first patterned metal layer. The second patterned metal layer is disposed on the insulating layer in the pixel region, and includes a source and a drain. The passivation layer is disposed on the second patterned metal layer and the insulating layer. A top surface of the source is in contact with the passivation layer, and the conductive protection layer is disposed on the drain.

Pixel structure, array substrate and method of fabricating the same

A pixel structure includes a substrate, a gate line, a data line, a semiconductor pattern, a non-metal source electrode pattern, a non-metal drain electrode pattern, and a pixel electrode. The gate line and the data line are disposed on the substrate. The semiconductor pattern is disposed on the gate line, and the semiconductor pattern overlaps two corresponding edges of the gate line along a vertical projective direction. The non-metal source electrode pattern and the non-metal drain electrode pattern are disposed on the semiconductor pattern. The non-metal source electrode pattern and the non-metal drain electrode pattern are respectively disposed on two corresponding edges of the gate line. The non-metal source electrode pattern is partially disposed between the data line and the gate line. The pixel electrode is electrically connected to the non-metal drain electrode pattern.

Pixel structure and manufacturing method thereof

A method for manufacturing a pixel structure is provided. A thin film transistor is formed on a substrate and an insulating layer is formed to cover the substrate and the thin film transistor. The insulating layer is patterned by a half-tone mask to form a protruding pattern, a sunken pattern connecting the protruding pattern, and a contact window inside the sunken pattern. A transparent conductive layer is formed to cover the protruding pattern and the sunken pattern, and filled in the contact window. A passivation layer is formed to cover the transparent conductive layer. A pixel electrode pattern is formed from the transparent conductive layer by removing a part of the passivation layer located on the protruding pattern, a part of the transparent conductive layer on the protruding pattern, and a part of the passivation layer located within the contact window. A pixel structure manufactured by the method is provided.

A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation layer; a pixel electrode and a connecting electrode. The data line does not overlap the scan line. The passivation layer disposed on the source electrode and the drain electrode includes a first contact hole partially exposing the drain electrode, and a plurality of second contact holes partially exposing the data line or the scan line. The pixel electrode disposed on the passivation layer is electrically connected to the drain electrode through the first contact hole. Furthermore, the connecting electrode disposed on the passivation layer is electrically connected to the data line or the scan line through the second contact holes.

Pixel structure and method of fabricating the same

A manufacturing method for a thin film transistor (TFT) is provided. In the manufactured TFT, after a source structure, a drain structure and a channel structure are formed, a first photoresist layer is not removed and a second photoresist is formed on the first photoresist layer through which a semiconductor structure is formed. Further, n-type amorphous silicon, poly silicon or an organic metallic compound is used in replace of the conventional metal to form the source and drain structures so as to reduce step number of manufacturing for the TFT.

Manufacturing method for thin film transistor

This invention provides a lithographic process for multi-etching steps by using single reticle, wherein the develop step is performed next to a bake step after the photoresist layer has been exposed, such that a photoresist residue is formed on the peripheral region around a transformed pattern of the photoresist. Because the photoresist residue has thinner thickness compared to the photoresist layer, this kind of developed photoresist layer can be used as the very mask for multi-etching steps.

Lithographic process for multi-etching steps by using single reticle

A process of producing a thin film transistor includes forming a gate line on a substrate by first exposure and development processes. A source electrode, a drain electrode and a semiconductor channel are formed by second exposure and development processes. An island-shaped transistor is formed by third exposure and development processes. A protection layer with a contact hole therein is formed by fourth exposure and development processes. A pixel electrode is formed by fifth exposure and development processes to connect to the contact hole.

Process of manufacturing thin film transistor

A manufacture method of a pixel structure is provided. A gate is formed over a substrate, and a gate insulator layer is formed over the substrate covering the gate. A semiconductor layer is formed over the gate insulator layer and a metal layer is formed over the semiconductor layer. A first mask layer is formed on the metal layer, and the metal layer is patterned to form a source/drain by using the first mask layer as etching mask. Afterward, a second mask layer is formed on the first mask layer and further covers a region between the source/drain. The semiconductor layer is patterned by using the first and second mask layers as etching mask, and then the first and second mask layers are removed. A passivation layer is formed over the substrate. A pixel electrode is formed on the passivation layer. The pixel electrode is electrically connected with the drain.

Growing community of inventors

Changhua County, Taiwan

Chin-Tzu Kao