Macronix International Co., Ltd.

Chin-Tsan Yeh

Chin-Ta Su

Kuang-Chao Chen

Yung-Tai Hung

Tuung Luoh

Ta-Hung Yang

Ming-Da Cheng

Bing-Lung Yu

Ling-Wu Yang

Chun-Fu Chen

Tung-Han Chuang

Chih-Hsien Lo

A memory device is provided. A first conductive layer, a first diffusion barrier layer, a phase change layer, a second diffusion barrier layer and a second conductive layer are disposed on a first electrode layer in sequence to form a stacking structure. A dielectric layer is disposed on the first electrode layer and covers a sidewall of the stacking structure and part of a top surface of the second conductive layer. A second electrode layer is disposed on the dielectric layer and the second conductive layer. Barrier enhancing components are provided between a bottom surface of the first diffusion barrier layer and a top surface of the second diffusion barrier layer. Further, a method of manufacturing a memory device is provided.

Memory device and method of manufacturing the same

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.

Semiconductor structure and method for manufacturing the same

A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Isolation structure, non-volatile memory having the same, and method of fabricating the same

A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.

Method of forming a semiconductor device

A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.

Conductor removal process

A method of forming a non-volatile memory cell is provided. The method comprises: (a) providing a substrate; (b) forming a stacking structure on the substrate, the stacking structure at least comprising an oxide-nitride-oxide layer (ONO layer) and a polysilicon layer thereon; (c) patterning the stacking structure to form a plurality of separated stacking units, each two stacking units having an aperture therebetween; (d) forming a source region and a drain region buried in the substrate at two sides of the each stacking unit; (e) forming an oxide layer in the aperture and over the stacking units; and (f) performing a chemical mechanical polishing (CMP) process to remove the oxide layer over the stacking units and outside the aperture.

Growing community of inventors

Hsinchu, Taiwan

Chin-Tsan Yeh