Himax Technologies, Inc.

Ncku Research and Development Foundation

Chi Mei El Corporation

Chin-Tien Chang

Ying-Lieh Chen

Chien-Ru Chen

Lin-Kai Bu

Chuan-Che Lee

Hong-Ru Guo

Yu-Wen Chiou

Chien-Hung Tsai

Jia-Hui Wang

Tzong-Yau Ku

Hui-Min Wang

Hung-Yu Huang

Meng-Tse Weng

Wei-Kai Tseng

Ching-Chung Lee

Hsin-Chia Su

Jia-Hao Wu

Chen-Song Yen

Jen-Wen Cheng

Hsu-Yu Hsiao

A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to one another. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and at least one latch signal to the source drivers based on the lock signal. The source drivers respectively output a plurality of pixel voltages to the display panel according to the latch signal. The training packets and the color data packets are serially transmitted to the source drivers.

Display and operating method thereof

A source driver including a controller, a plurality of flip-flops, a plurality of shift registers and a plurality of driving channels is provided. The controller extracts control information from an image data stream. Each of the flip-flops respectively receives a corresponding control bit of the control information, and output the corresponding control bit. The shift registers correspond to the flip-flops one by one, and sequentially transmit an enable pulse. Each of the shift registers determines whether to output the enable pulse according to the control bit outputted by the corresponding flip-flop. The driving channels correspond to the shift registers one by one. Each of the driving channels switches an operation state into an enable mode or a disable mode according to the enable pulse outputted by the corresponding shift register.

Source driver and display device

A source driver for driving at least one sub-pixel is disclosed, in which the source driver includes a gamma voltage generator and a digital to analog converter. The gamma voltage generator generates a plurality of gamma voltages, in which the gamma voltage generator includes a first gamma resistor string and an operation circuit. The first gamma resistor string includes a plurality of resistors electrically connected serially for dividing a first gamma reference voltage and a second gamma reference voltage into the gamma voltages. The operation circuit optionally adds increments to the gamma voltages according to a timing control signal, wherein the increments are the same when the gamma voltages are added. The digital to analog converter selecting one of the gamma voltages generated by the operation circuit as a driving voltage based on received digital pixel data.

Source driver for driving at least one sub-pixel

A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module.

Source driver

A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.

Buffering circuit with reduced dynamic power consumption

An output buffering circuit of a driver device for a display includes a first amplifier circuit having a first input stage, coupled between an upper power supply and a lower power supply, and a first output stage, coupled between the upper power supply and a first intermediate power supply that is greater than the lower power supply, and a second amplifier circuit having a second input stage coupled between the upper power supply and the lower power supply, and a second output stage coupled between a second intermediate power supply that is lower than the upper power supply and the lower power supply.

Output buffering circuit, amplifier device, and display device with reduced power consumption

A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Wafer and test method thereof

A source driver includes at least a channel, and the channel includes an N-type digital-to-analog converter (NDAC) and an operational amplifier. The NDAC is utilized for receiving input data and selecting one of a plurality of gamma voltages to generate output data according to the input data. The operational amplifier is coupled to the NDAC, and is utilized for amplifying at least the output data to generate an amplified output data. In addition, the channel does not include any P-type digital-to-analog converter.

Source driver not including any P-type digital-to-analog converter

An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V) and a second voltage (V) are applied on the upper buffer, and a third voltage (V) and a fourth voltage (V) are applied on the lower buffer, wherein V&#x3e;V, V&#x3e;V, V&#x3e;V, and V&#x3e;V. Then, the upper buffer is operated to output data to a plurality of pixels thereby operating the liquid crystals of the pixels over an upper supply range, wherein the upper supply range is from Vto V. Thereafter, the lower buffer is operated to output data to the pixels thereby operating the liquid crystals of the pixels over a lower supply range, wherein the lower supply range is from Vto V

Output buffer of a source driver applied in a display

An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage.

Output buffer with slew-rate enhancement output stage

A lighting emitting display, a pixel circuit and a driving method thereof. The pixel circuit includes a driving transistor, a capacitor and a LED. The capacitor receives a first supply voltage and is coupled to a gate of the driving transistor. A cathode of the LED receives a second supply voltage. During a pre-charge period, the gate and the drain of the driving transistor are coupled to an anode of the LED, the source of the driving transistor is coupled to a charging voltage. The source of the driving transistor receives a data signal and the drain and gate of the driving transistor are coupled to each other during a programming period. The source of the driving transistor is coupled to receive the first supply voltage and the drain of the driving transistor is coupled to the anode of the LED during a display period.

Lighting emitting display, pixel circuit and driving method thereof

The present invention discloses an apparatus for driving a display in which each pixels of the display receives a driving voltage and a common voltage, and a luminance of each pixel is determined by a difference between the received driving voltage and the common voltage. The apparatus comprises a plurality of source driver chips, each of which receives a pixel value and generates the driving voltage corresponding to the pixel value according to a plurality of Gamma voltages, wherein at least one of the Gamma voltages is generated by one of the source driver chips.

Apparatus for driving a display and gamma voltage generation circuit thereof

An OLED display and pixel circuit thereof are provided. The pixel circuit includes first and second switches, first and second PMOS transistors, a capacitor and an OLED. The first switch, controlled by a first scan signal, has a first end receiving a data signal and a second end. The second switch, controlled by a second scan signal, has a third end coupled to the second end and a fourth end. The first PMOS transistor has a source coupled to a high voltage, a drain coupled to the fourth end and a gate coupled to the second end. The second PMOS transistor has a gate coupled to the second end and a source coupled to the high voltage. The capacitor is coupled to the gate of the first PMOS transistor and the high voltage. The OLED has a positive end coupled to a drain of the second PMOS transistor.

Organic light emitting diode display and pixel circuit thereof

A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip

A luminescent display device is disclosed. The luminescent display device is comprised of an array of pixels, a first driving chip and a second driving chip. The array of pixels is comprised of columns and rows of pixels. The first driving chip is connected a first pixel of the array of pixels, and the second driving chip is connected to a second pixel of the array of pixels. The second pixel is adjacent to the first pixel. The first driving chip is not connected to all pixels in a row of the at least one row of pixels.

Growing community of inventors

Tainan County, Taiwan

Chin-Tien Chang