Powertech Technology Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Ta Wu

Kun-Chi Hsu

Shih-Chun Chen

Sheng-Tou Tseng

Ting-Yeh Wu

Ying-Lin Chen

Chia-Shiung Tsai

Yeur-Luen Tu

Chi-Hsin Lo

Yuan-Hung Liu

Tsung-Hsun Huang

Chi-Sheng Chang

Hsiu Ouyang

I-Lin Chan

Cheng-Hao Ciou

Chui-Liang Chiu

Jen-Tung Tseng

Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.

Semiconductor packaging structure with back-deposited shielding layer and manufacturing method thereof

A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.

Chip carrier device

A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.

Semiconductor package having partial outer metal layer and packaging method thereof

A wafer storage device includes a wafer cassette and a carrier plate. The wafer cassette includes a housing and a plurality pairs of retaining members disposed on lateral walls of the housing. The carrier plate is placed into the housing, is supported by one pair of the retaining members, and includes a plate body carrying the wafer thereon, and having a periphery formed with two slots extending respectively in two different radial directions of the wafer. Two positioning members respectively and radially correspond in position to the slots, and abut against an outer rim of the wafer.

Wafer storage device, carrier plate and wafer cassette

A wafer processing method uses a chuck table with smaller diameter than a semiconductor wafer to be processed. A cut through edge trimming is therefore implemented on the periphery of the semiconductor wafer to form a cut through straight side at the periphery and also form a flat portion at the periphery as a positioning means for taping and backside grind processes.

Wafer processing method with full edge trimming

A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.

Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence

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Hsinchu, Taiwan

Chin-Ta Wu