United Microelectronics Corp.

Au Optronics Corporation

Microtek International Inc.

Chin-Sheng Yang

Tsai-Yu Wen

Chen-Hsien Hsu

Wei-Jen Wang

Chien-Fu Chen

Wen-Sheng Chien

Zhi-Hong Huang

Cheng-Yang Tsai

Cheng-Tsung Ku

Chao-Wei Lin

Yu-Cheng Tung

Chien-Hung Chen

Yu-Ren Wang

Bin-Siang Tsai

Ming-Jui Chen

Tsuo-Wen Lu

Chia-Wei Huang

Chun-Jen Chen

Tan-Ya Yin

Yu Shu Lin

Chun Jen Chen

Chien-Ting Lin

Che-Hua Hsu

Li-Wei Cheng

Chun-Yen Liu

Guang-Hwa Ma

Ming-Shing Chen

Horng-Nan Chern

Yi-Nan Su

Wei-Ting Wu

Ming-Hui Chang

Chorng-Lih Young

Guan-Ru Huang

Derek Tang

Wenhung Hsieh

Ying-Chou Lai

The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Integrated circuits with standard cell

The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

Static random access memory unit structure

The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.

A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.

Semiconductor device and method of forming the same

A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Nanowire and method of fabricating the same

A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.

Semiconductor device formed with nanowire

Static random access memory layout structure

A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

Sonos device

Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Semiconductor device and operating method thereof

A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top portion of the fin to form a fin recess and depositing a germanium-based semiconductor into the fin recess as a germanium-based plug. The method comprises etching the shallow trench structure to expose the germanium-based semiconductor side faces. The exposed germanium-based semiconductor undergoes annealing to form high carrier mobility nanowire structures. The nanowire structures can also be formed of different diameters by selective oxidation of some of the deposited germanium-based plugs. Alternately, forming fin structures of different widths results in deposited germanium plugs of different widths to be deposited to form different thicknesses of nanowires.

Method for forming nanowire and semiconductor device formed with the nanowire

Sonos device and method for fabricating the same

An integrated circuit configuration includes a substrate, a diffusion region, a gate structure, an extension conductor structure, a dielectric layer, a contact structure, and a metal conductor line. The diffusion region is formed in the substrate. The gate structure is formed over the substrate and spanned across the diffusion region. The extension conductor structure is formed over the semiconductor substrate and contacted with the diffusion region. The extension conductor structure is extended externally to a first position along a surface of the substrate, wherein the first position is outside the diffusion region. The dielectric layer is formed over the substrate, the gate structure and the extension conductor structure. The contact structure is penetrated through the dielectric layer to be contacted with the first position of the extension conductor structure. The metal conductor line is formed on the dielectric layer and contacted with the contact structure.

Integrated circuit configuration having extension conductor structure and fabricating method thereof

A pixel circuit of a light emitting diode display includes a light emitting diode, six transistors and two capacitors. The effect of the variation of the threshold voltage of the transistor in the pixel circuit on the display quality can be improved through supplying specific the first to fourth control signals and the first to third reference voltages to the pixel circuit. A light emitting diode display using the aforementioned pixel circuit and a driving method of the aforementioned pixel circuit are also provided.

Pixel circuit, light emitting diode display using the same and driving method thereof

Growing community of inventors

Hsinchu, Taiwan

Chin-Sheng Yang