Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Ming Fu

Tsung-Che Lu

Chih-Hsien Chang

Yu-Tso Lin

Mao-Ruei Li

Wei Chih Chen

Tsung-Hsin Yu

Chih-hsien Chang

Chi-Chang Lu

Chung-Hui Chen

Ruey-Bin Sheen

Cheng-Hsiang Hsieh

Wan-Te Chen

Tzu Ching Chang

A semiconductor component for a memory device is provided. The semiconductor component comprises a first active region extending in a first direction; a second active region extending in the first direction; a first conductive layer disposed across the first active region and the second active region, in a second direction substantially perpendicular to the first direction; a second conductive layer extending in the first direction; and a first conductive via connecting the first conductive layer and the second conductive layer.

Semiconductor circuit for memory device and method of manufacturing the same

A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.

Sense amplifier and method thereof

A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.

Method of fabricating semiconductor devices having different architectures and semiconductor devices fabricated thereby

Method and apparatus for optimizing circuit design are disclosed. In one aspect, the method includes receiving a circuit design of an integrated circuit and identifying a first circuit design of a first subsystem of the IC and a second circuit design of a second subsystem of the IC. The first subsystem operates on a plurality of digital variable signals and the second subsystem operates on a plurality of analog variable signals. The method also includes synthesizing a first HDL netlist based on the first circuit design, synthesizing a second HDL netlist based on the second circuit design, and obtaining behaviors of the circuit design of the IC using a single HDL-based simulator with both the first HDL netlist and the second HDL netlist as inputs.

Apparatus and method of optimizing an integrated circuit design

A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.

Gated tri-state inverter, and method of operating same

An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.

Impedance measurement circuit and impedance measurement method thereof

A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

System and semiconductor device therein

The disclosure provides a voltage droop monitor (VDM) and a voltage droop monitoring method. The method includes: receiving a first reference clock signal and delaying the first reference clock signal as a first clock signal; delaying the first clock signal as a corresponding second clock signal; receiving the corresponding second clock signal from the corresponding first DCDL and generating a corresponding third clock signal via modifying a phase of the corresponding second clock signal; receiving the corresponding third clock signal; receiving a second reference clock signal; and collectively outputting a TDC code combination based on the second reference clock signal and the corresponding third clock signal, wherein the TDC code combination varies in response to a voltage variation of a to-be-monitored voltage.

Voltage droop monitor and voltage droop monitoring method

The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

Delay estimation device and delay estimation method

A phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage.

Growing community of inventors

Zhubei, Taiwan

Chin-Ming Fu