Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Min Huang

Hua-Tai Lin

Chia-Cheng Chang

Cherng-Shyan Tsay

Chien Wen Lai

Shun-Shing Yang

Lun-Wen Yeh

Bo-Han Chen

Chi-Ming Tsai

Chien-Wen Lai

Jia-Guei Jou

Ching-Hung Lai

Yin-Chuan Chen

Wei-Kuan Yu

Tsai-Ming Huang

Kong-Beng Thei

Shih-Ming Chang

Hung-Chang Hsieh

Ming-Hui Chih

Wen-Chen Lu

Lai Chien Wen

Yen-Hsu Chu

Chern-Shyan Tsay

Jau-Shian Liang

A method for forming a photomask includes following operations. A first photomask is received. The first photomask includes a first pattern and a first scattering bar. The first photomask is used to remove a first portion of a target layer to form a first opening and a second opening. The first opening corresponds to the first pattern, and the second opening corresponds to the first scattering bar. A second photomask is received. The second photomask includes a second pattern. The second photomask is used to remove a second portion of the target layer to form a third opening. The third opening corresponds to the second pattern. The second opening is widened to form the third opening using the second photomask.

Photomask and method for manufacturing photomask and semiconductor structure thereof

Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Method and apparatus for integrated circuit mask patterning

A method for forming a photomask is provided. The method includes: receiving an initial layout, the initial layout comprising a first pattern and a second pattern; decomposing the initial layout into a first layout including the first pattern and a second layout including the second pattern; inserting a third pattern into the first layout; overlapping the first layout including the first pattern and the third pattern to the second layout including the second pattern; increasing a width of the third pattern in the first layout overlapping the second pattern in the second layout to form a fourth pattern in the first layout; and outputting the first layout comprising the first pattern, the third pattern and the fourth pattern into a first photomask.

A method for forming a photomask is provided. The method includes: receiving an initial layout including a plurality of first patterns and a plurality of second patterns; decomposing the initial layout into a first layout including the plurality of first patterns and a second layout including the plurality of second patterns; inserting a plurality of third patterns into the first layout, wherein each of the plurality of third patterns is adjacent to at least one of the plurality of first patterns; comparing the first layout and the second layout; identifying a fourth pattern as an overlapping portion of the plurality of third patterns overlapping one of the plurality of second patterns; increasing a width of the fourth pattern; and outputting the first layout including the first patterns, the third patterns and the fourth patterns into a first photomask.

Method for manufacturing photomask and semiconductor thereof

Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process.

Photolithography scattering bar structure and method

Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Method of lithographic process evaluation

The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.

OPC method with higher degree of freedom

One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.

Structure for chip extension

Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.

Growing community of inventors

Taichung, Taiwan

Chin-Min Huang