National Semiconductor Corporation

Chin-Miin Shyu

Constantin Bulucea

Prasad Chaparala

Chih Sieh Teng

Fu-Cheng Wang

Abdalla Aly Naem

Hung-Sheng Chen

Farrokh Mohammadi

C S Teng

A fuse target is fabricated in a copper process by forming a number of copper targets at the same time that the copper traces are formed. After the copper targets and the copper traces have been formed, metal targets, such as aluminum targets, are formed on the copper targets at the same time that metal bonding pads, such as aluminum bonding pads, are formed on the copper traces.

Fuse target and method of forming the fuse target in a copper process flow

At least one source/drain zone (or) of an enhancement-mode insulated-gate field-effect transistor (or) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (M,M,M, orM) and a more lightly doped lower portion (L,L,L, orL) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value Vwhen the channel length is at a value L, are at least 0.03 volt less than Vwhen the channel length is approximately 0.3 &#x3bc;m greater than L, and materially decrease with increasing channel length when the channel length is approximately 1.0 &#x3bc;m greater than L.

Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

The source/drain zones (andorand) of a p-channel IGFET (or) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (M,M,M, orM) and a more lightly doped lower portion (L,L,L, orL) underlying, and vertically continuous with, the main portion.

P-channel field-effect transistor with reduced junction capacitance

An IGFET ( or ) has a channel zone ( or ) situated in body material ( ). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones ( and or and ) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones ( and or and ) of a p-channel IGFET ( or ) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Fabrication of p-channel field-effect transistor for reducing junction capacitance

Silicon controlled rectifier (SCR) structures are provided that are triggered by lightly doped diffusion (LDD) junction breakdown voltages of approximately 4-10 V. The SCR structures eliminate the need for the field plate diode and resistor secondary protection elements found in conventional SCR-based ESD protection circuits, thus minimizing RC delay on the signal line and reducing circuit size. The SCR structures are compatible with existing CMOS processes and are scalable to submicron technology.

Low voltage triggering silicon controlled rectifier structures for ESD

A structure and method of fabricating same is provided for a deep junction, non-self-aligned MOS transistor for suppressing hot carrier injection. According to the invention, dopant is introduced into a semiconductor substrate of a first conductivity type to form first and second spaced-apart substrate regions of opposite conductivity in the substrate. The first and second regions will become the source and drain regions of a deep junction, non-self-aligned MOS transistor having an effective channel length less than about 3.5 microns. The junction depth of the source and drain regions is greater than about 4000 Angstroms. Next, a layer of dielectric material is formed over the substrate. A region of conductive material is then formed over the dielectric material to serve as the gate of the MOS device. The resulting deep junction device has improved reliability as compared to self-aligned MOS devices of comparable effective channel length.

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San Jose, CA, United States of America

Chin-Miin Shyu