Nan Ya Technology Corporation

Chin-Lung Chu

Po-Chun Lin

The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

Semiconductor apparatus and method for preparing the same

The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

Method for preparing a semiconductor apparatus

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

Semiconductor method for forming semiconductor structure having bump on tilting upper corner surface

A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.

Semiconductor structure

A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.

Combing bump structure and manufacturing method thereof

A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.

Stacked semiconductor structure

Semiconductor structure having bump on tilting upper corner surface

The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure is used to be electrically connected to a power terminal or a ground terminal.

A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on the semiconductor substrate. The conductive layer is disposed on the pad. The solder bump is disposed on the conductive layer. The at least two metal side walls are disposed along opposing outer side walls of the solder bump respectively.

A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.

Die device, semiconductor device and method for making the same

A semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

A semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical bump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

Semiconductor package with lateral bump structure

The present disclosure provides a semiconductor apparatus having a plurality of semiconductor dies stacked in a face-to-face manner and a method for preparing the same. By stacking dies having different functions vertically in a face-to-face manner, a face-to-face communication is implemented between the dies having different functions. In addition, stacking the dies having different functions vertically in a face-to-face manner reduces the occupied area of the semiconductor apparatus, as compared to a semiconductor apparatus with dies having different functions arranged in a laterally adjacent manner. Furthermore, the signal path of the dies having different functions vertically stacked in the face-to-face manner is shorter than the signal path of the dies having different functions arranged in a laterally adjacent manner; consequently, the dies having different functions vertically stacked in the face-to-face manner of the present disclosure can be applied to high-speed electronic devices.

A semiconductor chip includes a semiconductor device with an upper surface and a lower surface opposite to the upper surface. The semiconductor device includes an input terminal, a plurality of through silicon vias, a plurality of selection pads, a plurality of tilt pads and a plurality of tilt conductive structures. The through silicon vias are extended through the semiconductor device. The selection pads are located on the lower surface The tilt pads are located on the upper surface and connected to the selection pads through the through silicon vias respectively. Each tilt pad includes a pad surface that is non-parallel to the upper surface. A lower end of each tilt conductive structure is in contact with the pad surface of each tilt pad, and an upper end of each tilt conductive structure is vertically overlapped with an immediately-adjacent one of the tilt pads.

Growing community of inventors

Taoyuan, Taiwan

Chin-Lung Chu