United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Lung Chen

Han-Min Huang

Victor Chiang Liang

Chu Fu Chen

Chun-Yao Lee

Chi-Feng Huang

Chia-Chung Chen

Ming-Tsung Tung

Chia-Cheng Pao

Wei-Chun Chang

Wen-Kuo Li

Hung-Te Lin

Shing-Ren Sheu

Mingo Liu

Jung-Ching Chen

Hong-Ze Lin

Wei-Shan Liao

Bo-Jui Huang

Chun Hao Liao

Kun-Yi Chou

Ting-Zhou Yan

Chin-Hung Liu

Chun-Ching Yu

Tzyy-Jye Lin

A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

Transistor having asymmetric threshold voltage and buck converter

A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.

Transistor having asymmetric threshold voltage, buck converter and method of forming semiconductor device

An integrated circuit device includes a lightly doped region such as the base region of a bipolar junction transistor within a semiconductor body. The device further includes a UV barrier layer formed over the lightly doped region. The UV barrier protects the lightly doped region from damage that can occur during high energy plasma etching or UV irradiation to erase EPROM.

UV protection for lightly doped regions

A manufacturing method of an anti punch-through leakage current MOS transistor is provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Manufacturing method of anti punch-through leakage current metal-oxide-semiconductor transistor

An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Anti punch-through leakage current metal-oxide-semiconductor transistor and manufacturing method thereof

A lateral-diffusion metal-oxide-semiconductor device includes a semiconductor substrate having at least a field oxide layer, a gate having a layout pattern of a racetrack shape formed on the substrate, a common source formed in the semiconductor substrate and enclosed by the gate, and a drain surrounding the gate and formed in the semiconductor substrate. The gate covers a portion of the field oxide layer. The common source includes a first doped region having a first conductive type and a plurality of islanding second doped regions having a second conductive type. The drain includes a third doped region having the first conductive type. The third doped region overlaps a portion of the field oxide layer and having an overlapping area between the third doped region and the field oxide layer.

Lateral-diffusion metal-oxide-semiconductor device

A method of fabricating a semiconductor device utilizes a substrate including a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. A first well of a first conductivity type is formed. Two separate second wells of a second conductivity type are formed in the first well and two separate isolation structures are formed respectively in the second wells in each of the high voltage circuit area and the medium voltage circuit area. A first gate dielectric layer is formed in the high voltage circuit area. A second gate dielectric layer that is thinner than the first gate dielectric layer is formed in each of the medium voltage circuit area and the low voltage circuit area. A gate is formed. Two source and drain regions of the second conductivity type are respectively formed. The method is simple and low-cost and meets the market requirement.

Method of fabricating semiconductor device

A semiconductor device includes a substrate of a first conductivity type, a first doped region of a second conductivity type, at least one second doped region of the first conductivity type, a third doped region of the second conductivity type, a gate structure, and at least one contact. The first and the second doped regions are configured in the substrate, and each second doped region is surrounded by the first doped region. The third doped region is configured in the substrate outside of the first doped region. The gate structure is disposed on the substrate between the first and third doped regions. The contact is disposed on the substrate. Each contact connects, in a direction parallel to the gate structure, the first and second doped regions alternately.

Semiconductor device and method for fabricating the same

A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region.

LDMOS with N-type isolation ring and method of fabricating the same

A semiconductor device including a substrate, a high voltage device, a medium voltage device and a low voltage device is provided. The substrate includes a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. The high voltage device, the medium voltage device and the low voltage device are respectively disposed in the high voltage circuit area, the medium voltage circuit area and the low voltage circuit area. The medium voltage device and the high voltage device have the same structure while the medium voltage device and the low voltage device have different structures. Further, the high voltage device, the medium voltage device and the low voltage device respectively include a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer.

Semiconductor device and method of fabricating the same

The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with a device isolation region in between. A channel region is situated between the first and second field oxide layers. A gate oxide layer is provided on the channel region. A gate is stacked on the gate oxide layer. A device isolation diffusion layer is provided in the device isolation region.

High-voltage metal-oxide-semiconductor device and method of manufacturing the same

A laterally diffused metal-oxide-semiconductor (LDMOS) device as well as a method of making the same is disclosed. A gate is formed on a semiconductor substrate between a source region and a drain region with one side laterally extending onto a part of a field oxide layer and the opposite side beside the source region. A gate dielectric layer is formed between the gate and the semiconductor substrate, wherein the gate dielectric layer comprises two or more portions having different thicknesses arranged laterally in a way that the thicknesses of the portions gradually increase from one side beside the source doping region to the opposite side bordering the field oxide layer. With such structure, the hot carrier impact is minimized and the gate length can be scaled down to gain I.

Laterally diffused metal-oxide-semiconductor device and method of making the same

An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length 'A' extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length 'L' extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.

IC chip

A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region. The via hole exposes the first patterned metallic layer. A metallic barrier layer is formed over the substrate. Ions are implanted into coded regions in the substrate. A second patterned metallic layer is formed in the peripheral circuit region to cover the second dielectric layer and fill the via hole. A third patterned metallic layer is formed in the memory cell region to fill the contact opening. A passivation layer is formed over the substrate.

Growing community of inventors

Hsinchu County, Taiwan

Chin-Lung Chen