National Chip Implementation Center National Applied Research Laboratories

National Applied Research Laboratories

National Chip Implementation Center

Other

Industrial Technology Research Institute

National Central University

Chin-Long Wey

Chun-Ming Huang

Chien-Ming Wu

Ying-Zong Juang

Shih-Lun Chen

Chi-sheng Lin

Chih-Chyau Yang

Chi-Shi Chen

Ji-Jan Chen

Wen-Ching Wu

Hann-Huei Tsai

Chin-Fong Chiu

Chen-Fu Lin

Liang-Chia Cheng

Pei-Wen Luo

Chih-Chyan Yang

Wei-De Chien

Chi Sheng Lin

Jwu-E Chen

Ting Hsu Chien

A safety-critical smart battery management system with the capability of charging single battery cells and discharging battery pack, which comprises smart battery pack, a smart battery charging module and a smart battery discharging module. In the smart battery pack, many cells in a battery group are charged separately at a time. The smart battery discharging module is used to discharge the smart battery pack, so as to achieve the efficacy of a promoted charging efficiency, an increased overall energy source efficiency, and a prolonged battery lifetime. The mechanism has plugging and automatic electric disconnection. Whenever a safety issue or a not-in-use state presents, the smart battery discharging module may be automatically separated with a load. The cells may be avoided from a self-discharging, which successively causes fire catching and thus an explosion and adversely affects a lifetime of the cells, thereby promoting a safety and reliability of the battery system.

Safety-critical smart battery management system with the capability of charging single battery cells and discharging battery pack

A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.

Hydrogen ion-sensitive field effect transistor and manufacturing method thereof

A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

Three-dimensional SoC structure formed by stacking multiple chip modules

A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

Multi-layer SoC module structure

A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.

Yield evaluating apparatus and method thereof

An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2&#x3c0;. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Edge-missing detector structure

The present invention discloses a carrier structure of a System-on-Chip (SoC) with a custom interface. The carrier structure includes a substrate, at least one common die, at least one custom interface and a molding compound. The common die and the custom interface are disposed on the substrate. The molding compound is used to package the common die which electrically connects to the substrate and the custom interface respectively. The carrier structure which includes the common die can form a complete SoC by connecting to an expansive die through the custom interface. The carrier structure with the common die which can be tested and certified in advance allows reducing and simplifying the developing procedures of the SoC.

Carrier structure of SoC with custom interface

Growing community of inventors

Hsinchu, Taiwan

Chin-Long Wey