Sigmatel, Inc.

Chin-Long Lin

Ren-Yuh Wang

Methods and systems for image processing are provided. A particular method includes receiving a video object plane (VOP) at an image processing device and decoding the received VOP. The method also includes storing an order number of the decoded VOP at a P-VOP queue in a memory of the image processing device when the received VOP is a predictive coded VOP (P-VOP). The method further includes storing the order number of the decoded VOP at a first available location of a display ordered read queue in the memory of the image processing device when the received VOP is not a P-VOP.

Method for determining display order of VOPS in decoder end or MPEG image system and device for executing the same

A device and a method are disclosed for motion estimation and bandwidth reduction in a memory. The device includes a memory for storing a plurality of frame data, a controller connected to the memory, a first motion estimation processor for performing a coarse-tuning operation and a second motion estimation processor for performing a fine-tuning operation. Similarity between a reference frame and a current frame is calculated based on the averages of every two adjacent pixels in the reference macroblocks and current macroblocks. The amount of calculations for determining motion estimation is greatly reduced, and bandwidth in utilizing the memory is accordingly reduced as motion estimation is advantageously achieved.

Method for motion estimation and bandwidth reduction in memory and device for performing the same

The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bus allows access by one of the functional devices for one cycle of period of time, a plurality of request agents corresponding to the functional devices, a control register respectively storing access priority grades for the request agents, a plurality of counter timers respectively loading the access priority grades; and a bus elector coupled with the counter timers wherein the bus elector respectively compares the loaded access priority grades and elects one out of the request agents according to the compared access priority grades. The memory bus accordingly allows access by one of the functional devices corresponding to the elected request agent for one cycle of period of time.

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San Jose, CA, United States of America

Chin-Long Lin