United Microelectronics Corp.

Chin-Lai Chen

Water Lur

Tony Lin

Jih-Wen Chou

Meng-Jin Tsai

A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.

MOS transistor with two empty side slots on its gate and its method of formation

A method for forming shallow trench isolation without a recessed edge problem is disclosed. The present invention comprises forming a pad oxide layer on a substrate. Next, a silicon nitride layer is formed on the pad oxide, and a sacrificial layer is formed on the silicon nitride layer. A photo-resist layer that defines an active region on the sacrificial layer is applied. Thereafter, the portions of the sacrificial layer, the silicon nitride layer, the pad oxide layer and the substrate are removed to form a trench. Portions of the silicon nitride layer are undercut, and a dielectric layer is formed to fill the trench. The dielectric layer is planarized until the silicon nitride layer is exposed. Finally, the silicon nitride layer and the pad oxide layer are removed.

Growing community of inventors

Taoyuan Hsien, Taiwan

Chin-Lai Chen