Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Kun Wang

Chia-Ming Tsai

Liang-Chen Chi

Miin-Jang Chen

Chun Hsiung Tsai

Yu-Min Chang

Jian-An Ke

Tsan-Yao Chen

Jhih-Jie Huang

Yuan-Chang Huang

Chen-Hua Douglas Yu

Ying-Lang Wang

Chee-Wee Liu

Wei-Cheng Wang

Yuh-Ta Fan

Wei-Fan Lee

Lu-Min Liu

Chih-Hsiung Huang

Chang Yung Cheng

Iman Hsu

Hsueh-Shih Fu

Cheng-Cheng Chang

Li-Tien Huang

Miin-Jang Cheng

Keng-Ham Lin

Wei-Lun Jian

Tzu-Yao Lin

Lu-Min Lin

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate over the substrate and a gate dielectric layer between the gate and the substrate. The gate dielectric layer includes an oxide-inhibiting layer having a dielectric constant greater than about 8 and being in an amorphous state.

Semiconductor devices, FinFET devices and methods of forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and an interfacial layer formed over the substrate. The semiconductor structure further includes a gate structure formed over the interfacial layer. In addition, the interfacial layer is made of metal germanium oxide, metal silicon oxide, or metal germanium silicon oxide and is in direct contact with a top surface of the substrate.

Semiconductor structure with interfacial layer and method for manufacturing the same

Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Epitaxial growth of doped film for source and drain regions

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate. The method includes forming a buffer layer over the semiconductor substrate. The buffer layer is in an amorphous state. The method includes nitriding the buffer layer into a nitride buffer layer. The method includes forming a gate dielectric layer over the nitride buffer layer. The method includes performing a thermal annealing process to convert the gate dielectric layer into a crystalline gate dielectric layer. The method includes forming a gate electrode over the crystalline gate dielectric layer.

Method for forming gate dielectric layer

A semiconductor device and methods of formation are provided. A semiconductor device includes a dielectric film over a dielectric layer. The dielectric film includes a crystalline structure having a substantially uniform composition of zirconium, nitrogen and oxygen. The dielectric film is formed through in situ nitrogen plasma doping of a zirconium layer. The dielectric film functions as a gate dielectric. The dielectric film has a high dielectric constant between about 28-29 and has a low leakage current density of about 4.79&#xd7;10A/cm. The substantially uniform distribution of nitrogen throughout the zirconium oxide of the dielectric film increases the k value of the dielectric film by between about 15% to about 17% as compared to a dielectric film that has a non-uniform distribution of nitrogen through a zirconium oxide layer.

Method of forming semiconductor device

A semiconductor substructure with improved performance and a method of forming the same is described. The semiconductor substructure includes a dielectric film over a substrate, the dielectric film including at least one metal dielectric layer, at least one oxygen-donor layer, and at least one nitride-incorporation layer.

In-situ nitridation of gate dielectric for semiconductor devices

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer layer and a gate electrode over the crystalline gate dielectric layer.

Mechanisms for forming gate dielectric layer

A method for forming a dielectric film is disclosed. The method includes (a) exposing a substrate to a first gas pulse having a first oxygen-containing gas in a chamber; (b) exposing the substrate to multiple consecutive second gas pulses having a second oxygen-containing gas in the chamber, wherein the first oxygen-containing gas is different from the second oxygen-containing gas; and (c) sequentially after (a) and (b), exposing the substrate to a third gas pulse having a metal-containing gas in the chamber. Steps (a), (b), and (c) may be repeated any number of times to form the dielectric film with a predetermined thickness.

Method of forming dielectric films using a plurality of oxidation gases

Structures and methods for reducing backside polysilicon peeling are disclosed. A structure includes a substrate having a first side and a second opposite side, a first dielectric layer on the second side of the substrate extending in a direction from an edge of the substrate towards a center of the substrate, a high-k layer on the first dielectric layer, and a polysilicon layer on the high-k layer. The first dielectric layer has a first innermost sidewall relative to the center of the substrate, and the high-k layer has a second innermost sidewall relative to the center of the substrate. The second innermost sidewall is within 2 millimeters from the first innermost sidewall in a direction parallel to the second side. The polysilicon layer extends towards the center of the substrate further than the first innermost sidewall.

Substrate backside peeling control

Aspects of the present disclosure provide a method and a system for providing a selection of golden tools for better defect density and product yield. A golden tool selection and dispatching system is provided to integrate different components for robust golden tool selection and dispatching. The golden tool selection system selects a set of golden tools based on performance of a set of manufacturing tools and provides a fully automated operational environment to produce a product using the set of golden tools.

Method and system for providing a selection of golden tools for better defect density and product yield

A planarization process, featuring removal of spin on glass, used to fill narrow spaces between metal lines, has been developed. A dual dielectric, of underlying silicon oxide, and overlying silicon nitride, are initially used to passivate the metal lines, followed by the spin on glass fill. A RIE etchback of the spin on glass proceeds to a point in which the silicon nitride, on the metal line, is exposed. The exposed silicon nitride is then removed leaving a silicon oxide passivated metal line, and seamless insulator filled spaces. The ability of not exposing the passivating silicon oxide to RIE echback process, allows seamless fills to result.

Optimized planarization process for SOG filled vias

An improved structure and a process for forming an interlevel dielectric layer having a low capacitance between closely spaced metallurgy lines is provided. The method begins with a substrate surface having closely spaced metallurgy lines. A silicon oxide dielectric layer having a closed void between adjacent metallurgy lines is formed using electro cyclotron resonance techniques. The voids in the silicon dioxide dielectric layer are formed by controlling the ECR process parameters to achieve a proper etch to deposition ratio. The etch to deposition ratio of the silicon oxide layer is adjusted to the particular height and spacing between the metallurgy lines. Next, a spin-on-glass layer is formed over the silicon oxide dielectric layer. Portions of the SOG layer are etched back or chemically mechanically polished. The void (air) has a lower capacitance than the ECR silicon oxide layer. Therefore, the void in the silicon oxide dielectric layer reduces the capacitance of the layer, and in particular reduces the capacitance between metallurgy lines in the same level, which increases device performance.

Method for forming a low capacitance dielectric layer

A method is described wherein topography of semiconductor wafer surfaces is improved. This is accomplished by introducing a specific planarization technique after the deposition of the first level of metal. It is shown further that the technique involves a combination of oxide and spin-on-glass layers. The resulting dielectric system is etched back in such a way that the resulting two-tiered metal-oxide structure and the surface thereover offers a uniformly flat depth-of-field which in turn makes possible the use of submicron optolithographic tools for the ultra high density integrated circuit chips. In an attempt to improve further the required flatness for submicron technologies, it is shown that silicon nitride may be introduced at a judiciously chosen process step so as to minimize the propagation of surface irregularities from one layer to another through minimizing the so-called microloading effect. It is found that the presence of silicon nitride for this purpose also serves the purposes of eliminating, what are called, the 'exploding vias'.

Growing community of inventors

Hsinchu, Taiwan

Chin-Kun Wang