Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Kai Liu

Ruey-Yun Shiue

Pi-Chen Shieh

Wen-Teng Wu

Fouriers Tseng

Pei-Fen Chou

Chih-Jian Chen

Jun-Yean Chiou

Han-Shun Lui

A method of forming a SIMS monitor device for determining a doping profile of a semiconductor device structure including providing a plurality of regularly repeating semiconductor structures including a doping profile to form a monitor device including at least one layer of the regularly repeating semiconductor structures; planarizing the monitor device through a thickness of the regularly repeating semiconductor structures to reveal a target surface overlying the doping profile to form a monitor pattern; and, sputtering the target surface over a sputtering area including the monitor pattern through a thickness thereof while simultaneously detecting and counting over a time interval at least one type of species ejected from the target surface according to a secondary ion mass spectroscopy procedure (SIMS).

Method and apparatus for determining two dimensional doping profiles with SIMS

The present invention provides a method for identifying failure sites on a defective IC chip by utilizing a glass substrate equipped with a heating device and then coating a liquid crystal material layer on top. The liquid crystal device can be positioned in contact, or immediately adjacent to a surface of an IC device to be detected. After the liquid crystal temperature is raised to just below its transition temperature, a voltage signal can be fed into the IC device to trigger an overheating at a short or leakage to raise the liquid crystal material immediately adjacent to the short or leakage to a temperature above its transition temperature. Hot spots are thus produced to appear as bright spots for easy identification under an optical microscope.

Method and apparatus for identifying failure sites on IC chips

A method/system is provided for performing a design review checking operation and analyzing the resultant data. Perform a DRC operation describing chip features and generating flags for violation sites including patterns and paths. Execute pattern analysis and grade classification steps for the violation sites. Generate a vector array for each chip feature for each of the violation sites. Compare the vector arrays to determine whether degrees of similarity of geometries of chip features of violation sites meet one of a set of criteria. Classify the violation sites into classes with similar criteria. Select representative arrays from each class of violation sites to provide an output. Calculate distance from a violation site from the origin in a two-dimensional array. Give a grade to each vector array to indicate the level of seriousness of the rule violation by the site. Use a layout viewer to view the error flags generated by pattern analysis and grade classification steps.

Efficient design rule check (DRC) review system

An observable sample mounting fixture for mounting an IC specimen to a protective substrate is provided. In the sample mounting fixture, a base portion and a top portion are provided which are integrally connected together with a cavity therein-between for receiving a specimen. The base portion is further provided with an observation window such that the state of cure of an adhesive layer between a substantially transparent substrate and the IC specimen can be observed in real time. During an early observation, i.e., when the sandwiched structure is only cured for 2-5 minutes, the sandwiched structure can be easily disassembled when bubbles are observed. By utilizing the present invention novel sample mounting fixture, valuable test specimens can be saved for providing valuable quality control and reliability data. The sample mounting fixture is further constructed with a compression means which includes a shaft, a coil spring, a handle and a compression foot for contacting the IC specimen during a curing process of the sandwiched structure.

Real time observable sample mounting fixture

A new method is provided for the creation of interfacing and adjacent surfaces when creating damascene interconnects. Under the first embodiment of the invention, the surface area of the Intra Metal Dielectric (IMD) in which the copper metal pattern has been created is partially removed thereby reducing and sub-dividing the surface area of the interfacing surface. Under the second embodiment of the invention, the surface area of the IMD is sub-divided into a multiplicity of squares that now form the interfacing surface area. Under the third embodiment of the invention, the surface area of the Intra Metal Dielectric (IMD) in which the copper metal pattern has been created is essentially removed leaving sidewalls of the IMD material on the formed pattern of copper interconnects.

Stress relieve pattern for damascene process

The present invention discloses a method for preparing thin specimens suitable for physical analysis of a semiconductor microstructure by an instrument such as a transmission electron microscope. The method can be practiced by first forming support structures in a low density material medium for shielding a higher density material to be analyzed such that materials having different densities may be removed in a subsequent ion milling process at approximately the same milling rate with the lower density material supporting the higher density material during the ion milling process.

Method for preparing thin specimens consisting of domains of different

The present invention discloses a novel method and apparatus for de-etching pin-holes in a passivation layer that is deposited over a metal conductor layer on the surface of a semiconductor wafer by utilizing a substantially clear, electrically conductive film as a top electrode immersed in an electrolyte for observing under an optical microscope bubbles generated from a pin-hole on the wafer surface which functions as a bottom electrode when a DC current is flowing through the top electrode, the electrolyte and the bottom electrode such that gases in the form of bubbles are generated at the pin-hole site where metal is exposed to the electrolyte.

Method and apparatus for detecting pin-holes in a passivation layer

A bond pad structure and method of forming the bond pad structure which provides for reliable interconnections between the bond pad structure and the next level of circuit integration. The bond pad structure uses three metal pads separated by layers of dielectric. Via plugs are formed between the first and second metal pads and between the second and third metal pads. The via plugs are formed in a diamond shape with respect to the metal pads. The metal pads are squares with the same orientation. The periphery of the via plugs forms a square rotated 45.degree. with respect to the square metal pads.

Growing community of inventors

Hsin-Chu, Taiwan

Chin-Kai Liu