American Telephone & Telegraph Co., At&t Bell Laboratories

Chin-Jen Lin

Kevin D Kolwicz

Che-Tsung Chen

Won J Yoon

Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.

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South Whitehall, PA, United States of America

Chin-Jen Lin