United Microelectronics Corp.

Chin-Hui Lee

Chih-Cheng Liu

Chien-Hua Tsai

Ting-Chi Lin

Chuan-Fu Wang

Benjamin Szu-Min Lin

Jung-Chao Chiou

Tzu-Min Cheng

The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole. Finally, a spacer is formed using an insulating material on the walls of the node contact hole to complete the node contact hole. The spacer completely covers the walls of the two bit lines within the node contact hole but the surface of the silicon substrate exposed at the bottom of the node contact hole is not completely covered by the spacer.

Method of forming a node contact hole on a semiconductor wafer

The present invention provides a method of forming a passivation layer of a DRAM on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, and two adjacent gates positioned on the surface of the silicon substrate wherein each gate comprises a spacer on each of two opposite walls. The method comprises forming a first silicon-oxygen-nitride layer of predetermined thickness on the semiconductor wafer, forming a second silicon-oxygen-nitride layer of predetermined thickness on the first silicon-oxygen-nitride layer and forming a BPSG (borophosphosilicate glass) layer uniformly on the second silicon-oxygen-nitride to planarize the surface of the semiconductor wafer. The BPSG layer is used as a dielectric layer. The first silicon-oxygen-nitride layer serves as diffusion barrier layer to prevent diffusion of boron and phosphorous from the BPSG layer into the silicon substrate. The second silicon-oxygen-nitride layer is used as an etching stop layer. The first and the second silicon-oxygen-nitride layers together constitute the passivation layer of the DRAM. The extinction coefficient of the first layer is smaller than that of the second layer, and the extinction coefficient of the first and the second layers is between 0.3 and 0.8.

Method of forming a passivation layer of a DRAM

The present invention relates to a method of forming a level silicon oxide layer on a semiconductor wafer. The semiconductor wafer comprises a substrate having a first region containing no silicon nitride on its surface and a second region which is higher than the first region and contains a silicon nitride layer on its surface. The method comprises performing a cleaning process on the semiconductor wafer with an alkaline solution to uniform the deposition rate over the surface of the first region; and performing a deposition process employing ozone as a reactive gas with a flow capacity of 80-200 g/L to form a silicon oxide layer above the first and second regions wherein the deposition rate of the silicon oxide layer on the first region is higher than that on the second region and the silicon oxide layer above the first region is leveled with that above the second region after a predetermined period of time.

Method of forming a level silicon oxide layer on two regions of different heights on a semiconductor wafer

The invention relates to an ion implantation method for adjusting the threshold voltage of MOS transistors. The MOS transistor is employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprises a substrate, a gate insulating layer positioned on the substrate, and a gate conducting layer with a rectangular-shaped cross section positioned on the gate insulating layer. The method comprises performing an ion implantation process at a predetermined dosage and ion energy to implant dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the superficial portion of the substrate below the gate insulating layer.

Method of ion implantation for adjusting the threshold voltage of MOS transistors

The present invention provides a method of depositing a silicon oxide layer on a semiconductor wafer. The semiconductor wafer comprises a plurality of transistors positioned on its surface. The method comprises performing a cleaning process on the semiconductor wafer by using an alkaline solution to make a more uniform deposition rate of the silicon oxide layer on the transistors and other areas over the surface of the semiconductor wafer, then performing a deposition process by employing ozone as a reactive gas to form a silicon oxide layer of even thickness and without voids.

Method of depositing a silicon oxide layer on a semiconductor wafer

The present invention provides a method of forming a contact hole in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a silicon--oxygen layer positioned on the silicon substrate, and a photoresist layer positioned on the silicon--oxygen layer. An anisotropic dry-etching process is performed to vertically remove the silicon--oxygen layer below the opening to a predetermined depth to form the contact hole which contains a polymer layer on its surface. A soft-etching process is performed to remove the polymer layer in the contact hole. The dry-etching process and soft-etching process are performed alternatively to vertically remove the silicon--oxygen layer under the contact hole until the surface of the silicon substrate can be reached through the contact hole.

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Taipei, Taiwan

Chin-Hui Lee