Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Hsiung Hsu

Huang-Yu Chen

Wen-Hao Chen

Chung-Hsing Wang

Yuan-Te Hou

Tsong-Hua Ou

Li-Chun Tien

Hui-Zhong Zhuang

Lee-Chung Lu

Yi-Kan Cheng

Ken-Hsien Hsieh

Chin-Chang Hsu

Cheng-I Huang

Wen-Ju Preet Yang

Pin-Dai Sue

Ru-Gun Liu

Ting Yu Chen

Hsiao-Shu Chao

Meng-Kai Hsu

Ching Fu Chang

Yen-Pin Chen

Ho Che Yu

Yi-Chuin Tsai

Hung Lung Lin

Fang-Yu Fan

Ying-Yu Shen

Jhih-Jian Wang

Godina Ho

A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

Method of cutting conductive patterns

A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Cell boundaries for self aligned multiple patterning abutments

A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

Stitch and trim methods for double patterning compliant standard cell design

Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.

Layout boundary method

A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

Layout method and system for multi-patterning integrated circuits

A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.

Method and system for multi-patterning layout decomposition

Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.

Multiple via connections using connectivity rings

A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Cell layout design and method

A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Compression method and system for use with multi-patterning

A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit.

Routing method

Systems and methods are provided for designing semiconductor device layouts. For example, an initial layout including multiple target features associated with semiconductor devices is received. One or more dummy features are determined to be inserted into the initial layout. The target features and the dummy features are assigned to multiple masks based at least in part on one or more mask-assignment rules. A final layout is generated for fabricating the semiconductor devices.

Systems and methods for designing layouts for semiconductor device fabrication

Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises one or more original pattern portions assigned pattern colors that correspond to pattern masks. One or more new pattern portions within the new layout are assigned pattern colors such that the new layout has a relatively high color similarity with respect to the original layout. In this way, changes to the pattern masks are reduced, thus mitigating fabrication delay or costs that would otherwise result from significant changes to the pattern masks.

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Guanyin, Taiwan

Chin-Hsiung Hsu