Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Hao Su

Hsi-Kuei Cheng

Der-Chyang Yeh

Ying-Lang Wang

Hsing-Kuo Hsia

Chih-Ping Chao

Hsien-Ping Feng

Hung-Ju Chien

Shih-Tzung Chang

Chu-Chang Chen

Hsun-Chang Chan

Hao-Hsun Lin

A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.

Multiple silicide integration structure and method

An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.

Semiconductor devices having post passivation interconnections and a buffer layer

A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Method for reducing defects in post passivation interconnect process

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Hsin-Chu, Taiwan

Chin-Hao Su