Altera Corporation

Other

Intel Corporation

Chin Ghee Ch'ng

Wei Yee Koay

Tony K Ngai

Boon Jin Ang

Ting Lu

Ket Chiew Sia

Sean Woei Voon

Eu Geen Chew

Ching Kooi Hor

An integrated circuit includes a comparator circuit that generates a control signal based on a comparison between a threshold voltage and a supply voltage. The integrated circuit also includes a clock signal generation circuit that generates a clock signal and that receives the control signal. The clock signal generation circuit decreases a frequency of the clock signal to a reduced frequency in response to the control signal indicating that the supply voltage has decreased below the threshold voltage. The integrated circuit also includes a secure device manager circuit that has a timing circuit. The clock signal is provided to a clock input of the timing circuit. The timing circuit receives supply current from the supply voltage. The secure device manager circuit performs a security function for the integrated circuit using the timing circuit in response to the clock signal with the reduced frequency.

Techniques for preventing voltage tampering of security control circuits

Integrated circuits with memory cells are provided. The memory cells may be arranged in rows and columns. Each column of memory cells may be coupled to a respective pair of data lines. The data lines may be precharged using precharge circuitry. The precharge circuitry may include n-channel precharge transistors, an equalizer transistor, an isolation transistor, a pull-down transistor, a voltage booster, and control logic. The voltage booster may provide boosted voltage signal for overdriving the n-channel transistors by pulsing a control signal. During first pulse of the control signal, the data lines may be charged up to an intermediate voltage level. During second pulse of the control signal, the data lines may be charged up to a positive power supply voltage level that is greater than the intermediate voltage level. Performing double boosted data line precharge in this way can help reduce leakage and improve memory performance.

Methods and apparatus for performing boosted bit line precharge

An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.

Interface circuitry for an integrated circuit system

Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.

Memory circuitry with dynamic power control

Growing community of inventors

Gelugor, Malaysia

Chin Ghee Ch'ng