Taiwan Semiconductor Manufacturing Comp. Ltd.

Chin-Chou Liu

Po-Hsiang Huang

Fong-yuan Chang

Yi-Kan Cheng

Chin-Her Chien

Sheng-Hsiung Chen

Yun-Han Lee

Fong-Yuan Chang

Ka Fai Chang

Hui Yu Lee

Cheng-Hung Yeh

Lee-Chung Lu

Chi-Yu Lu

Pin-Dai Sue

William Wu Shen

Yen-Hung Lin

Wei-Pin Changchien

Nan-Hsin Tseng

Chao-Yang Yeh

Bo-Jr Huang

Chung-Sheng Yuan

Hui-Zhong Zhuang

Sandeep Kumar Goel

Sen-Bor Jan

Chun-Chen Chen

Ching-Fang Chen

Jung-Chou Tsai

Chung-Te Lin

Chung-Hsing Wang

Mill-Jer Wang

Jerry Chang Jui Kao

Hui-Yu Lee

Chih-Lin Chen

Chi Wei Hu

Saurabh Gupta

Li-Chun Tien

Hung-Chih Lin

Yuan-Te Hou

Wan-Yu Lo

Meng-Kai Hsu

Ji-Jan Chen

Kuan-Yu Lin

Chi-Wei Hu

Noor Mohamed Ettuveettil

Hsiu-Chuan Shu

Ming-Fa Chen

Wei-Cheng Wu

Yi-Wei Chen

Hsien-Hsin Sean Lee

Chung-Min Fu

Huan Chi Tseng

Lie-Szu Juang

Yi-Kuang Lee

Kin Lam Tong

Noor E V Mohamed

Shuo-Mao Chen

Kuo-Nan Yang

Yi-Lin Chuang

Keh-Jeng Chang

Shao-Yu Wang

Kai-Ming Liu

Chih-Chia Chen

Wan-Chun Chen

Yu-Jen Chang

Chin-Yuan Huang

Kai-Yun Lin

Chien-Hui Chen

Hsiang-Ho Chang

Aftab Alam Khan

Chun-Cheng Ku

Pei-Ying Lin

Meng-Hsueh Wang

Tom Chen

Wei-Pin Changchein

Yao-Hsien Tsai

Tong Kin Lam

Tai-Yu Wang

Ta-Wen Hung

Ming-Ke Tsai

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Integrated circuit device with improved layout

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method and system for generating layout diagram including wiring arrangement

The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.

Through-silicon via in integrated circuit packaging

A system (for generating a layout diagram of a wire routing arrangement) includes a processor and memory including computer program code for one or more programs, the system generating the layout diagram including: placing, relative to a given one of masks in a multi-patterning context, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining that the first candidate location results in an intra-row non-circular group of a given row which violates a design rule, the intra-row non-circular group including first and second cut patterns which abut a same boundary of the given row, and a total number of cut patterns in the being an even number; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

System and method for generating layout diagram including wiring arrangement

The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Heat dissipation structures for three-dimensional system on integrated chip structure

A cell region of a semiconductor device, the cell region including: components (representing a first circuit) including alpha info conductors and dummy conductors which are substantially collinear correspondingly with reference tracks, regarding the first circuit, the alpha info conductors beipng correspondingly for one or more input and/or output signals, or one or more internal signals, and for a majority of the reference tracks, first ends correspondingly of the alpha info conductors or the dummy conductors being aligned and proximal to a first side of the cell region; a first alpha info conductor being on a first reference track and being an intra-cell conductor which does not extend beyond the first side nor a second side of the cell region; and a portion of a first beta info conductor of a second circuit (represented by components of an external cell region) being on the first reference track.

Cell region including portion of conductor of another cell region and semiconductor device include the same

An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.

Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same

A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Layout design methodology for stacked devices

A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Method for manufacturing a cell having pins and semiconductor device based on same

A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.

3D IC power grid

Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Semiconductor device and method of manufacture

The present disclosure provides a method and a system for determining the equivalence of the DRM data set and the DRC data set. The system retrieves a DRM data set and a DRC data set, and transforms the DRM data set and the DRC data set into a first data structure node and a second data structure node respectively. The system determines whether the first data structure node and the second data structure node are equivalent according to a data structure node comparison model.

Method and system for determining equivalence of design rule manual data and design rule checking data

A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

System for generating layout diagram including wiring arrangement

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing, if there is a violation, placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method for generating layout diagram including wiring arrangement

Growing community of inventors

Jhubei, Taiwan

Chin-Chou Liu