Silicon Integrated Systems Corporation

Chin-Cho Tsai

Tien-Yueh Liu

Ching-Chang Shih

Kuo-Chung Huang

Ming-Mao Chiang

A method for multi-threshold voltage CMOS process optimization. The method includes the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation; obtaining a static timing analysis report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts; changing the devices whose setup time margins are less than Ts to low threshold devices; changing the devices whose setup time margins are greater than Tl to high threshold devices; checking a setup time of each device; changing the devices whose setup time margin does not meet the enhanced static timing analysis report; performing a first pocket implant process for the normal threshold devices; performing a second pocket implant process for the low threshold devices and performing a third pocket implant process for the high threshold devices.

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Keelung, Taiwan

Chin-Cho Tsai