Cadence Design Systems, Inc.

Silicon Perspective Corporation

Chin-Chi Teng

Wei-Jin Dai

Jui-Ming Chang

Pinhong Chen

Eddy Pramono

Chung-wen Tsao

To estimate path delays within an IC, a serial database is first created to hold and read out RC extraction data for nets within the IC in an order in which the RC extraction data will be needed when estimating path delays. Thereafter, as the RC extraction data is sequentially read out of the database for each net, the path delay though each section of the net is computed and added to the estimated path delay for each signal path including that net section. The RC extraction data for each net is accessed and accessed only once, thereby minimizing the processing time needed to perform timing analysis by minimizing hard disk read accesses when the RC extraction database resides on a hard disk.

Method of estimating path delays in an IC

A clock tree synthesis (CTS) tool determines how to position a hierarchy of buffers for fanning out a clock signal to clocked devices ('sinks') within an integrated circuit (IC). The tool first clusterizes the sinks and places a lowest level fan-out buffer near each cluster. The tool then iteratively places progressively higher level buffers by clusterizing a last-placed buffer level and then placing a next higher level buffer near the centroid of each lower level buffer cluster, until the tool has placed buffers at a mid-level for which variation in path distances between that level and a next higher buffer level exceeds a predetermined limit. The CTS tool then places a top level buffer at the centroid of the mid-level buffers, divides the layout into partitions, each containing a similar number of mid-level buffers, and then places a second-highest level buffer in each partition. The CTS iteratively places each next lower buffer level by dividing each partition into progressively smaller partitions and placing progressively lower level buffers in each smaller partition until it places buffers at a level having sufficient number of buffers to drive the mid-level buffers.

Two-stage clock tree synthesis with buffer distribution balancing

An RC extraction tool estimates capacitances of conductors residing along parallel grid lines on each of a set vertically stacked layers of insulating material of an IC based on data contained in a IC layout file describing positions of structures forming the IC. The tool initially processes the layout file to generate a separate database for each layer. Each database includes a separate table for each grid line on its corresponding layer, and each table includes a separate entry for each conductor residing along that grid line containing data indicating dimensions and a position of its corresponding conductor along that grid line. The tool processes the databases for each layer in ascending order to estimate capacitances between conductors on that layer and to generate set of data structures mapping the amount of conductor surface area on that layer to areas of layers above that layer, and to areas of layers below that layer in which conductors reside. The tool then processes the data structures to estimate capacitances between conductors on nearby layers.

IC conductor capacitance estimation method

A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.

Clock tree synthesis for mixed domain clocks

A clock tree synthesizer alters a clock tree design to balance a clock tree receiving and distributing one or more clock signals to many clocked devices (&ldquo;sinks&rdquo;) within an integrated circuit, wherein the clock tree includes one or more crossover and reconvergence points at outputs of multiplexers receiving clock signals via different paths through the clock tree. The clock tree synthesizer balances the clock tree by first balancing the subtree downstream of each multiplexer and then representing the multiplexer and the subtree with a separate macro for each multiplexer input, each macro representing the path delay from the corresponding multiplexer input to the sinks receiving clock signal inputs via the subtree. When the clock tree includes crossover points, the macros split the clock tree into a separate tree for each clock signal. The clock tree synthesizer then balances each resulting separate tree, and thereafter replaces the macros with the multiplexers and balanced subtrees they represent, thereby producing a single balanced clock tree for all of the distributed clock signals.

Clock tree synthesizer for balancing reconvergent and crossover clock trees

A method is disclosed for synthesizing a clock tree for a partitioned integrated circuit (IC) layout comprising a plurality of base level partitions and a top level partition each occupying a separate area of a semiconductor substrate. The base level partitions include syncs to be clocked by edges of a clock signal applied to an entry node within the area occupied by the top level partition. In accordance with the method, a plurality of independently balanced subtrees are separately synthesized. Each subtree resides within the area occupied by a separate base level partition and includes a start point at a perimeter of the area occupied by that base level partition and a network of buffers and signal paths for conveying a clock signal edge from the start point to each sync included within that area. Thereafter a top level portion of the clock tree is synthesized. The top level portion of the subtree resides within the substrate area containing the top level partition and conveys the clock signal from the entry point to the start point of each synthesized subtree.

Clock tree synthesis for a hierarchically partitioned IC layout

In an integrated circuit (IC) design, a set of K&times;N clocked IC devices (&ldquo;syncs&rdquo;) such as flip-flops and latches are organized into K clusters of N syncs each, with each cluster being clocked by a separate clock tree buffer. An improvement to a conventional &ldquo;K-center&rdquo; method for assigning syncs to clusters is disclosed. The improved method, which reduces the separation between syncs within the clusters, initially employs the conventional K-center method to preliminarily assign the K&times;N syncs to K clusters having N syncs per cluster. The improved method thereafter ascertains boundaries of rectangular areas of the IC occupied by the separate clusters. When areas of any group of M>1 clusters overlap, the K-center meth is repeated to reassign the set of M&times;N syncs included in e M overlapping clusters to a new set of M clusters. The new set of M clusters are less likely to overlap.

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Sunnyvale, CA, United States of America

Chin-Chi Teng