Macronix International Co., Ltd.

Macronix Internationalco., Ltd.

Chin-Cheng Yang

Chih-Hao Huang

Chi-Hao Huang

Hang-Ting Lue

Shih-Hung Chen

Hong-Ji Lee

Ching-Yu Chang

Yu-Wei Jiang

Chia-Hua Lin

Shou-Wei Huang

Ta-Hung Yang

Chun-Chung Huang

Cheng-Wei Lin

Chiao-Wen Yeh

Tzong-Hsien Wu

Tien-Chu Yang

Yun-Chu Lin

Yu-Lin Liu

Wei-Hung Wang

Lo-Yuen Lin

Chih-Haw Huang

Kuan-Cheng Liu

A semiconductor structure including a substrate and a pad structure is provided. The pad structure is located on the substrate. The pad structure includes material pairs and pads. The material pairs are stacked on the substrate to form a stair step structure. Each of the material pairs includes a conductive layer and a dielectric layer located on the conductive layer. Each of the pads includes a conductive pillar and a pad layer. The conductive pillar is embedded in the material pair and is connected to the conductive layer of the material pair. The pad layer is located on the conductive pillar.

Semiconductor structure and manufacturing method thereof

A routing pattern is provided. The routing pattern includes a first routing region, a second routing region and an interconnection region. The first routing region includes a plurality of first conductive lines extending along a first direction. The plurality of first conductive lines has a first pitch along a second direction perpendicular to the first direction. The second routing region includes a plurality of second conductive lines extending along the first direction. The plurality of second conductive lines has a second pitch along the second direction, and the second pitch is approximately equal to the first pitch. The interconnection region includes two body parts and a connecting part connecting to the body parts. The body parts are disposed separately along the first direction. A width of the connecting part along the second direction is smaller than a width of the body parts along the second direction.

Routing pattern

A memory device includes a staircase structure, multiple first plugs, multiple second plugs, and multiple third plugs. The staircase structure includes multiple gate layers and multiple insulating layers alternately stacked on each other, and the staircase structure includes multiple first blocks and multiple second blocks which alternate with each other. The first plugs are disposed in the first blocks, and the first plugs in a same first block are staggered with each other. The second plugs are disposed in the first blocks. The second plugs in a same first block are staggered with each other, and the first plugs and the second plugs in a same first block are staggered with each other. The third plugs are disposed in the second blocks.

Memory device and flash memory device with improved support for staircase regions

A method of fabricating a memory device includes patterning a stacked structure to form a first staircase structure and a second staircase structure; patterning a conductive layer under the stacked structure to form a first slit trench along a first direction; forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit; patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches, wherein the second slit trenches along a second direction perpendicular to the first direction; performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and filling a second dielectric layer in the second slit trenches to form multiple second slits.

Memory device and manufacturing method thereof

Reference marks for forming a staircase structure are disposed along slit areas of a 3D memory structure, and slits of the 3D memory structure are formed on the slit areas. In a staircase area, the reference marks are formed by etching the topmost one of stacked layers, having a pair of a dielectric layer and a sacrificial layer, in a stacked structure.

Semiconductor structure and method forming the same

A semiconductor device and method of fabricating the same are provided. The semiconductor device includes a substrate having a trench and an etching stop layer. The etching stop layer is disposed in the substrate and surrounds the bottom surface and a portion of a sidewall of the trench.

Semiconductor device having etching control layer in substrate and method of fabricating the same

A circuit structure comprises a plurality of first conducting lines extending in a first direction, the first conducting lines having a first pitch in a second direction orthogonal to the first direction; a plurality of linking lines extending in the second direction, the linking lines having a second pitch in the first direction, the second pitch being greater than the first pitch; and a plurality of connection structures connecting respective first conducting lines for current flow to respective linking lines, the connection structures each including a plurality of segments extending in the first direction, segments in the plurality of segments having a transition pitch in the second direction relative to adjacent segments in the plurality of segments greater than or equal to the first pitch, and less than the second pitch.

Layout design for fanout patterns in self-aligned double patterning process

A method for forming an aligned mask comprises etching a reference mark on a substrate to demarcate a boundary of an etch region; forming an etch mask on the substrate, using an exposure setting, the etch mask having a boundary; and measuring a distance between the reference mark and the boundary. When the measured distance is outside a margin of a target distance, then the etch mask is removed from the substrate, the exposure setting is changed, a next etch mask is formed using the changed exposure setting, and said measuring is repeated. A set of reference marks can be etched on a top level in a set of levels to demarcate boundaries of etch regions. An etch-trim process can be performed to form steps in the set of levels, wherein the etch-trim process includes at least first and second etch-trim cycles using first and second reference marks.

Method for forming an aligned mask

Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.

Interlevel connectors in multilevel circuitry, and method for forming the same

An edge structure for multiple layers of devices including stacked multiple unit layers includes first and second stair structures. The first stair structure is at a first direction of the devices where device contacts are formed, including first edge portions of the unit layers at the first direction, of which the borders gradually retreat with increase of level height. The elevation angle from the border of the first edge portion of the bottom unit layer to that of the top one is a first angle. The second stair structure includes second edge portions of the unit layers at a second direction. The variation of border position of the second edge portion with increase of level height is irregular. The elevation angle from the border of the second edge portion of the bottom unit layer to that of the top one is a second angle larger than the first angle.

Edge structure for multiple layers of devices, and method for fabricating the same

An interconnect structure including a first dielectric layer, a first conductive layer, a second conductive layer, a capping layer, and a via is provided. The first dielectric layer has a first trench and a second trench. The first conductive layer is located in the first trench. The second conductive layer is located in the second trench, and a top surface of the second conductive layer is lower than a top surface of the first dielectric layer. The capping layer having a via opening exposing a portion of the first conductive layer covers the first dielectric layer, the first conductive layer, and the second conductive layer. The via located on the first conductive layer and the first dielectric layer located between the first conductive layer and the second conductive layer is filled into the via opening and electrically connected to the first conductive layer.

Interconnect structure and fabricating method thereof

A structure of a patterned material layer including separate patterns arranged in rows and columns is described. The separate patterns in at least one row including the outmost row each have a larger dimension in the column direction than the separate patterns in the other rows. The separate patterns in at least one column including the outmost column each have a larger dimension in the row direction than the separate patterns in the other columns.

Patterned material layer and patterning method

A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.

Semiconductor device and critical dimension defining method thereof

A pad structure including a plurality of material pairs and a plurality of pads is provided. The material pairs are stacked on a substrate to form a stair step structure. A stair step of the stair step structure includes one of material pairs. Each of the material pairs includes a conductive layer and a dielectric layer on the conductive layer. Each of the pads is embedded in one stair step of the stair step structure and exposed by the dielectric layer corresponding to the one stair step and another stair step above the one stair step. A thickness of one of the pads is greater than a thickness of one of the conductive layers.

Pad structure and manufacturing method thereof

Disclosed herein are semiconductor devices and methods for fabricating a semiconductor device. In an embodiment, a method of fabricating a semiconductor device comprises providing a substrate. The method further comprises forming, on the substrate, an array region having a first height, a peripheral region having a second height greater than the first height, and a border region, the border region separating the array region from the peripheral region. The method further comprises forming a plurality of alternating insulative and conductive layers over at least a portion of the array region and the border region. The method further comprises forming a trench through the plurality of alternating insulative and conductive layers in at least a portion of the border region, the trench having sloping sidewalls.

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Hsinchu, Taiwan

Chin-Cheng Yang