United Microelectronics Corp.

Chi Mei Optoelectronics Corporation

Lam Research Corporation

Other

Chin-Cheng Chien

Chun-Yuan Wu

Chih-Chien Liu

Chin-Fu Lin

Chin-I Liao

Teng-Chun Tsai

Chiu-Hsien Yeh

Shu-Yen Chan

Ted Ming-Lang Guo

Hsiang-Ying Wang

Chan-Lon Yang

Chia-Lin Hsu

Tien-Wei Yu

Neng-Hui Yang

Tsai-Fu Hsiao

I-Ming Lai

Yu-Ren Wang

Tsuo-Wen Lu

Yu-Shu Lin

Ching-I Li

Ming-Hua Chang

Hsin-Kuo Hsu

Chao-Chun Chen

Shin-Chi Chen

Ling-Chun Chou

Szu-Hao Lai

Yu-Kun Chen

Teng-Chun Hsuan

Chien-Ting Lin

Shih-Hung Tsai

Chien-Liang Lin

Jei-Ming Chen

Chun-Wei Hsu

Chun-An Lin

Yu-Min Lin

Po-Yuan Chen

Chun-Hsien Lin

Jiunn-Hsiung Liao

Chieh-Te Chen

Tsai-Yu Wen

Chia-Lung Chang

I-Chang Wang

Shao-Wei Wang

Shin-Chuan Huang

Wen-Yi Teng

Wen-Jyh Sah

Cheng-Jen Chu

Tsung-Hung Chang

Guang-Yaw Hwang

Tzung-Ying Lee

Yeng-Peng Wang

Ya-Lun Cheng

Lien-Fa Hung

Yun-Cheng Kao

Ming-Yen Chien

Pau-Chung Lin

Ssu-I Fu

Kuo-Tai Huang

Hsin-Hung Chen

Ming-Sheng Yang

Zhi-Cheng Lee

Che-Hua Hsu

Chueh-Yang Liu

Cheng-Guo Chen

Yu-Ying Lin

Ying-Wei Yen

Wen-Tai Chiang

Tsung-Mu Yang

Yu-Wen Wang

Chih-Yueh Li

Tien-Chen Chan

Chun-Jen Chen

Ying-Tsung Chen

Shao-Hua Hsu

Ger-Pin Lin

Yi-Ching Wu

I-Cheng Hu

Chih-Chung Chen

Kuan-Yu Lin

Yun-San Huang

Chieh-Lung Wu

Chia-Hung Kao

Fong-Lung Chuang

Zhi-Jian Wang

Ching-Hong Jiang

Tsung-Yu Hou

An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.

Epitaxial process applying light illumination

A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

Fabricating method of a semiconductor device with a high-K dielectric layer having a U-shape profile

A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Semiconductor device having strained fin structure and method of making the same

The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

Manufacturing method of non-planar FET

The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

Non-planar FET

A cleaning process for oxide includes the following step. A substrate having a first area and a second area is provided. A first oxide layer is formed on the substrate of the first area and the second area. An ammonium hydroxide (NHOH) and hydrogen peroxide (HO) containing process is performed on the first oxide layer of the first area and the second area. A photoresist layer covers the first oxide layer of the first area while exposing the first oxide layer of the second area. The first oxide layer of the second area is removed. The photoresist layer is then removed.

Cleaning process for oxide

A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.

Method for fabricating semiconductor device with fin-shaped structure

A semiconductor structure includes a fin-shaped structure and a gate. The fin-shaped structure is located in a substrate, wherein the fin-shaped structure has a through hole located right below a suspended part. The gate surrounds the suspended part. Moreover, the present invention also provides a semiconductor process including the following steps for forming said semiconductor structure. A substrate is provided. A fin-shaped structure is formed in the substrate, wherein the fin-shaped structure has a bottom part and a top part. A part of the bottom part is removed to form a suspended part in the corresponding top part, thereby forming the suspended part over a through hole. A gate is formed to surround the suspended part.

Semiconductor structure and process thereof

A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.

Fabrication method for semiconductor devices

The present invention provides a method for forming a semiconductor structure, including the following steps: Firstly, a substrate is provided, the substrate has a first region defined thereon, a plurality of fin structure is disposed within the first region, and an insulating layer is disposed on the substrate and between each fin structure; next, a first material layer is then formed on the insulating layer, and the fin structures is exposed simultaneously, afterwards, the fin structure is partially removed, and an epitaxial layer is then formed on the top surface of each remained fin structure.

Method for forming semiconductor structure

A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

Strained silicon structure

A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.

Method of manufacturing semiconductor device having metal gate

A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Method of fabricating semiconductor patterns

A semiconductor device with fin-shaped structure is disclosed. The semiconductor device includes: a substrate; a fin-shaped structure on the substrate; and an epitaxial layer on a top surface and part of the sidewall of the fin-shaped structure, in which the epitaxial layer and the fin-shaped structure includes a linear gradient of germanium concentration therebetween.

Semiconductor device having fin-shaped structure and method for fabricating the same

A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

Semiconductor process for modifying shape of recess

Growing community of inventors

Tainan, Taiwan

Chin-Cheng Chien