Ncr Corporation

Chiman R Patel

Rolfe D Armstrong

Truc D Nguyen

Kasun K Chan

Victor F Cole

Jon M Corcoran

Henry Y Hsu

A star coupler device for interconnecting processors within a data processing system. The star coupler device includes first and second level star couplers. The first level star coupler includes a plurality of inputs and corresponding outputs and functions to logically OR together all signals received at its inputs to generate a first output signal. The second level star coupler also includes a plurality of inputs and corresponding outputs, one of the inputs to the second level star coupler being connected to receive the first output signal. The second level star coupler functions to logically OR together all signals received at its inputs, including the first output signal, to generate a second output signal which is provided at each of its outputs. A switch or multiplexer directs either the first or second output signal to each one of the outputs of the first level star coupler.

Star coupler device including means for connecting multiple star

A fault tolerant data processing system includes a pair of processors for simultaneously executing commands for processing data, a memory, and a data transmission bus between the processors and the memory voer which the processors may fetch data from and write data to the memory. A comparison circuit is included between the processors for comparing the data fetched and written by the processors. A rollback module is responsive to the comparison circuit for rolling back the operation of the processors to the beginning of a presently executing command in the event of a miscomparison by the comparison circuit.

Virtual command rollback in a fault tolerant data processing system

A prefetch circuit for use with a memory including a storage register for receiving a command from the memory, a decoding circuit for decoding the command to determine the identification of an index register contained within the command, and a fetch circuit for fetching the contents of the index register from the command. The prefetch circuit also includes a virtual address storage register for receiving and storing the virtual address of the command, an adding circuit for adding a predetermined offset to the virtual address of the command to obtain a new virtual address, a comparison circuit for determining if the new virtual address from the adding circuit has crossed a virtual page boundary, a transfer circuit responsive to the comparison circuit for transferring the real address in the real address storage register to the adding circuit for adding the offset thereto, thereby obtaining a new real address. The fetch circuit then fetches a prefetched command from the memory at the new real address. Data registers are also included for prefetching data.

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Escondido, CA, United States of America

Chiman R Patel