Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Chim Seng Seet

Taiebeh Tahmasebi

Kai Hung Alex See

Alex See

Liang Choo Hsia

Xuesong Rao

Juan Boon Tan

Vinayak Bharat Naik

Bei Chao Zhang

Zheng Zou

Kazutaka Yamane

Yun Ling Tan

Lei Wang

Wen Siang Lew

Wai Cheung Law

Huang Liu

Fan Zhang

Wei Lu

Hai Cong

Yeow Kheng Lim

Lup San Leong

Benfu Lin

Chenchen Jacob Wang

Tong Qing Chen

Chuan Chu Wang

Wen Zhan Zhou

Bo Tao

Yong Chiang Ee

Mei Sheng Zhou

Kangho Lee

Wanbing Yi

John Leonard Sudijono

Kiok Boone Elgin Quek

Dimitri Houssameddine

Khee Yong Lim

Kin Leong Pey

Tae Jong Lee

Liang-Choo Hsia

Yudi Setiawan

Kah Wee Gan

Alex K H See

Chun Hui Low

Chor Shu Cheng

Bo Yu

Kin Wai Tang

Michael Nicolas Albert Tran

Mei Zhen Ng

Kwee Liang Yeo

Jianhui Ye

San Leong Liew

Xiaohua Zhan

Hao Zhang

Meng Meng Chong

Jingyan Huang

Meng Meng Vanessa Chong

Hendro Mario

Aison John George

Rajesh Nair

Jyoti Gupta

Gerard Joseph Lim

Lai Lin Clare Yong

Grayson Dao Hwee Wong

Ju Dy Lim

A memory device may be provided, including a first planar electrode, a second planar electrode, and a switching element arranged between the first planar electrode and the second planar electrode to where a first side of the switching element is arranged over the first planar electrode and where a second side of the switching element is arranged under the second planar electrode. The switching element is thicker at the first side than the second side, and the switching element is configured to provide a conductive filament formation region.

Memory device having a switching element thicker at a first side than at a second side and method of forming the same

The present disclosure relates to semiconductor structures and, more particularly, to a thin film resistor and methods of manufacture. A structure includes: a thin film resistor having an opening and being between an upper insulator material and a lower insulator material; and a contact extending through the opening in the thin film resistor and into the lower insulator material.

Thin film resistor

According to various embodiments, a spin diode device may include a magnetic tunnel junction stack. The magnetic tunnel junction stack may include a lower magnetic layer, a tunnel barrier layer over the lower magnetic layer, and an upper magnetic layer over the tunnel barrier layer. The lower magnetic layer may include a lower magnetic film. The tunnel barrier layer comprising an insulating material. The upper magnetic layer may include an upper magnetic film. Each of the lower magnetic film and the upper magnetic film may have perpendicular magnetic anisotropy.

Spin diode devices

According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.

Integrated circuits and methods of forming integrated circuits

Memory cells and method of forming thereof are presented. The method includes forming a magnetic tunnel junction (MTJ) element which includes a fixed magnetic layer, a tunneling barrier layer and a composite free magnetic layer. The composite free magnetic layer includes an insertion layer between first and second free magnetic layers. The insertion layer includes an oxide or oxidized layer. The insertion layer increases the overall thickness of the free layer, decreasing switching current as well as thermal stability. The oxidized layer may be MgO or HfO. A surface layer may be provided over the oxide or oxidized layer to further enhance magnetic anisotropy to further decrease switching current. The surface layer is Ta, Ti or Hf.

Storage layer for magnetic memory with high thermal stability

A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.

Selective shielding of ambient light at chip level

A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.

Embedded memory in back-end-of-line low-k dielectric

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.

Integrated circuits with magnetic tunnel junctions and methods of producing the same

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.

A bottom pinned perpendicular magnetic tunnel junction (pMTJ) with high TMR which can withstand high temperature back-end-of-line (BEOL) processing is disclosed. The pMTJ includes a composite spacer layer between a SAF layer and a reference layer of the fixed magnetic layer of the pMTJ. The composite spacer layer includes a first non-magnetic (NM) spacer layer, a magnetic (M) spacer layer disposed over the first NM spacer layer and a second NM spacer layer disposed over the M layer. The M layer is a magnetically continuous amorphous layer, which provides a good template for the reference layer.

Composite spacer layer for magnetoresistive memory

A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.

Mram memory device and manufacturing method thereof

A magnetic memory having a base layer with a wetting layer and seed layer is disclosed. The wetting layer and seed layer promotes FCC structure along the (111) orientation to improve PMA. A surface smoother, such as a surfactant layer, is provided between the wetting and seed layers. This enhances the smoothness of the seed layer, resulting in smoother interface in the MTJ stack, which leads to improved thermal endurance.

Magnetic memory with high thermal budget

Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers and methods for making the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a copper bonding structure having a contact surface. The copper bonding structure overlies the substrate. A passivation layer formed of silicon carbon nitride is disposed on the contact surface.

Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers thereon and methods for fabricating same

Growing community of inventors

Singapore, Singapore

Chim Seng Seet