Arm Limited

Chiloda Ashan Senerath Pathirane

Allan John Skillman

Simon John Craske

Antony John Penton

David Michael Gilday

Robert Campbell Aitken

Ian Michael Caulfield

Vladimir Vasekin

Alan Jeremy Becker

Jean-Baptiste Brelot

Mittu Xavier Kocherry

An apparatus includes a processing pipeline comprising a plurality of stages, the plurality of stages including at least one instruction fusing stage to detect whether a block of instructions to be processed comprises a fusible group of instructions, and to generate a fused instruction to be processed by a subsequent stage of the processing pipeline when said block of instructions comprises said fusible group. However, when said block of instructions comprises a partial subset of said fusible group of instructions, the instruction fusing stage is configured to delay handling of said partial subset of said fusible group of instructions until the instruction fusing stage has determined whether at least one subsequent block of instructions to be processed comprises a remaining subset of instructions of said fusible group.

Fusion of instructions by delaying handling of a partial subset of a fusible group of instructions

A target apparatusfor debug includes a processing pipelinefor executing a sequence of program instructions. A debug interfacereceives debug command signals corresponding directly or indirectly to debug program instructions to be executed. An instruction bufferstores both the debug program instructions and non-debug program instructions. An arbiterselects between both the debug program instructions and the non-debug program instructions stored within the instruction buffer to form the sequence of program instructions to be executed by the processing pipeline. A complex coherent memory systemis shared by the debug program instructions and the non-debug program instructions such that they obtain the same coherent view of memory.

Executing debug program instructions on a target apparatus processing pipeline

A data processing apparatus includes a cache memory supporting parallel data loads involving both a first address and a second address. The first address is compared with TAG values stored within a first value store and the second address is compared in parallel with TAG values stored within a second value store. The second value store contains a proper subset of the data value stored within the first value store.

Parallel lookup in first and second value stores

A data processing apparatus includes error detection and correction circuitry with an associated hard-error memory buffer. When a correctable hard-error is detected associated with a memory access to a memory, if the hard-error memory buffer is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core and force the relinquishing of resources within other circuit elements such as a store buffer.

Malfunction escalation

An integrated circuit incorporates prefetch circuitry for prefetching program instructions from a memory. The prefetch circuitry includes a branch target address cache. The branch target address cache stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.

Branch target address cache using hashed fetch addresses

A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.

Memory built-in self-test for a data processing apparatus

This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an instruction to be processed by said data processor; a fetch unit responsive to an address input to said fetch unit to fetch an instruction stored at said address; an adder for adding a predetermined amount to said address stored in said register prior to sending said address to said fetch unit, said predetermined amount determining a position in a program flow said fetched instruction has with respect to said instruction addressed in said register; said adder being responsive to detection of a change in program flow to reset said predetermined amount to an initial value, and to increase said predetermined amount for subsequent fetches by an amount equal to the separation between addresses such that consecutive addresses are fetched up to a maximum predetermined amount.

Instruction fetching following changes in program flow

A data processing systemis provided with multiple processorswhich can operate in either a split-mode in which each processor executes its own program flow or a locked-mode in which the processors execute the same program flow. Debug circuitryis associated with each of the processors. In an emulation-locked mode of operation, one of the processorsis active and its respective debug circuitryis active to update the debug state data so as to debug the locked mode code. At the same time, the second processoris held inactive and its state is maintained as well as the debug state data of the debug circuitrywithin that inactive processor. This maintains the debug state data of the processoracross entry and exit to the locked mode of operation.

Debugging a multiprocessor system that switches between a locked mode and a split mode

A data processing apparatus is disclosed that comprises a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said values stored in said settable elements form an instruction or decoded instruction.

Initialisation of a pipelined processor

A multiple-processor systemis provided where each processor--can be dynamically switched between running in a locked mode where one processor-checks the operation of the other processor-and a split mode where each processor--operates independently. Multiple auxiliary circuits--provide auxiliary functions for the plurality of processors--. In the split mode, each auxiliary circuit--separately provides auxiliary functions for a corresponding one of the processors--. To ensure coherency when each processor--executes a common set of processing operations, in the locked mode a shared one of the auxiliary circuits-provides auxiliary functions for all of the processors--

Auxiliary circuit structure in a split-lock dual processor system

Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from the processor indicating whether the processor is currently processing an interrupt; a detection circuit for detecting an interrupt request and outputting an interrupt request signal to a data processing apparatus; disabling logic for disabling at least a portion of the detection circuitry; wherein in response to detecting the processor is currently processing an interrupt; the detection circuit is configured to detect a change in value of the interrupt signal caused by assertion of the interrupt signal indicating an interrupt request and to output an interrupt request signal to output circuitry in response to detecting the interrupt signal assertion; and in response to detecting the processor is not currently processing an interrupt; the disabling logic is configured to disable at least a portion of the detection circuit; and the detection circuit with the at least a portion disabled, is configured to output the interrupt signal as the interrupt request signal to the output circuitry.

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Cambridge, United Kingdom

Chiloda Ashan Senerath Pathirane