Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Chikayoshi Morishima

Tetsuya Watanabe

Yasunobu Nakase

Niichi Itoh

Shigeki Ohbayashi

Takashi Kuroi

Yoshinori Okumura

Masaru Haraguchi

Tokuya Osawa

Yoshihiro Yamashita

There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.

Semiconductor device and impedance adjusting method thereof

Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.

Semiconductor memory device allowing high-speed data reading

A 2-port SRAM includes a memory cell having: a latch circuit holding potential at storage nodes complementarily; access transistors arranged between the storage nodes and bit lines, respectively, and turned on in response to word lines being activated; a write access transistor and a storage level drive transistor arranged between the storage nodes, respectively, and a ground potential and turned on in response to a first one of the word lines being activated and a sub bit line, respectively, and a write access transistor turned on in response to a second one of the word line being activated and a storage level drive transistor turned on in accordance with a sub bit line.

Multiport semiconductor memory device capable of sufficiently steadily holding data and providing a sufficient write margin

A differential amplifier circuit includes a pair of first and second P-type transistors and a pair of first and second enhancement-mode N-type transistors. The first and second P-type transistors have respective gates each connected to the drain of the other P-type transistor, i.e., the first and second P-type transistors are cross-coupled. To respective gates of the first and second N-type transistors, a constant voltage VG (Vth&#x2266;VG&#x2266;Vdd) is applied. Currents of different magnitudes respectively are applied to first and second input terminals and the first and second N-type transistors generate voltages on first and second output terminals respectively, according to respective currents flowing through the first and second N-type transistors. The differential amplifier circuit is employed as a sense amplifier of a semiconductor memory device for use in reading data.

Differential amplifier circuit with high amplification factor and semiconductor memory device using the differential amplifier circuit

An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.

Static-type semiconductor memory device

A shared program circuit is provided for a plurality of memory circuits, and a select circuit is provided for selecting one of the memory circuits. The select circuit includes gate circuits for transmitting a program signal from the shared program circuit to the memory circuits, and a gate selector that activates one of the gate circuits. Thus, in a semiconductor integrated circuit device provided with a plurality of memory circuits, like an ASIC, chip area occupied by a program circuit for programming an address of a defective memory cell therein is reduced.

Semiconductor integrated circuit device with memory circuit

Among bit line pairs, the bit line adjacent to the bit line connected to a selected memory cell is maintained in the precharged state, and the bit lines in each pair are disposed sandwiching the bit line of another bit line pair. In a static semiconductor memory device, inter-bit-line interference in the memory cell data reading is reduced, and a changing rate of a bit line voltage amplitude is increased.

Semiconductor memory device with reduced interference between bit lines

A semiconductor memory device includes a plurality of column groups (memory blocks M to M ), a plurality of column selection circuits and a plurality of read/write circuits disposed in correspondence with the plurality of column groups, a redundancy selection circuit that selects connection to the read/write circuit by shifting the connection, and input/output circuits that selectively connect an input/output node of the redundancy selection circuit with the data input/output line.

Semiconductor memory device having a redundancy construction

Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions,to,and,to,and polysilicon regions,to,) of a memory cell for one memory cell unit of a memory cell array region,is identical to that of a dummy cell of a peripheral dummy cell region,and both patterns present a line symmetrical relationship with respect to a boundary line BC,In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region,is identical to that of a dummy cell of a power wiring region,and both patterns present a line symmetrical relationship with respect to a boundary line BC

Semiconductor device

During standby, bit lines BL,and /BL,are precharged, and the potentials of word lines WL,and WL,are set at a potential slightly higher than a ground potential. Since a stable retaining current flows through an access transistor into a node inside a memory cell holding the H level, the data can be retained with stability. Moreover, during an access, the selected word line is brought to the H level, while the unselected word lines are brought to a ground potential.

Semiconductor memory device with data retention characteristic of improved stability

Disclosed is an amplifier circuit comprising: an amplifier,which is activated when supplied with a control signal SE and which outputs a pair of amplified signals D and DC; a detection circuit,for detecting one of the pair of amplified signals D and DC being changed in potential and outputting a detection signal PO upon detection of the potential change; and a latching circuit,which receives a set signal S and the detection signal PO and which outputs the control signal SE. The latching circuit,starts outputting the control signal SE in response to an input of the set signal S and terminates the output of the control signal SE upon input of the detection signal PO.

Differential sense amplifier circuit

A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.

Semiconductor memory device permitting time required for writing data to be reduced

Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

In the semiconductor circuit device of the present invention, the switching circuit 10 connects the power supply pin 4 to the capacitance 9 before the input signal 2 to the semiconductor circuit 1 is changed so that the electric charge of the semiconductor 1 is stored in the capacitance 9, and when the input signal 2 is changed, the semiconductor circuit 1 is charged with the electric charge stored in the capacitance 9. And, after the input signal 2 is changed, the switching circuit 10 connects the power supply pin 4 to a power supply to charge the semiconductor circuit 1.

Semiconductor circuit device with reduced power consumption

A delay circuit (7) delays a transfer signal (V1) transferred through a transfer signal line (1) by the first delay time (dt1) to generate the first delayed signal (V9) and delays the first delayed signal (V9) by the second delay time (dt2) to generate the second delayed signal (V10). The second current mirror differential amplifier circuit (11) receives the transfer signal (1) and the second delayed signal (V10), whose ground terminal is connected to the first delayed signal line (9). On the other hand, the first current mirror differential amplifier circuit (14) also receives the transfer signal (V1) and the second delayed signal (V10), whose power-supply terminal is connected to the first delayed signal line (9). In response to a rise of the input signal (V1), the circuit (14) starts its operation to change a level of an output signal (V6) from 'L' level to 'H' level, remaining thereafter. After that, in response to a fall of the input signal (V1), the circuit (11) starts its operation to change the level of the output signal (V6) from 'H' level to 'L' level. With this configuration, a receiver circuit of a semiconductor circuit device achieves a faster operation and a lower power consumption.

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Hyogo, Japan

Chikayoshi Morishima