Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Chikara Gotanda

Yutaka Nio

Hideyo Uwabata

Hideto Nakahigashi

Toshiaki Kitahara

Yuichi Ishikawa

Yutaka Nishikawa

Takashi Yamaguchi

Atsushi Ishizu

Kouichiro Nagata

Miho Nagai

A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.

Digital interface decode receiver apparatus

An interpolation apparatus that generates interpolation pixel values necessary for converting input video data of interlace scanning into video data of progressive scanning is provided. A plurality of candidate pixel-pairs each of which is composed of two pixels that are symmetric with respected to a pixel that is going to be interpolated are selected from pixels on adjacent two scan lines within one field of the input video data, and a difference between pixel values of each selected pixel-pair is calculated. A pixel-pair to be used for generating the interpolation pixel value is determined, based on the smallest difference and the second smallest difference of the calculated differences. An interpolation pixel value of the pixel that is going to be interpolated is generated based on pixel values of the determined pixel-pair.

Interpolation apparatus, and video signal processing apparatus including the same

A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Horizontal deflection circuit and television receiver

A controller and a control method of an integrated memory provided in a system LSI used in television receiver or other video appliance are disclosed. In the memory controller of the invention, when a clock signal suspend command signal not synchronized with a synchronization signal is entered, a suspend command signal synchronized with the synchronization signal is generated. The clock signal supplied in the integrated memory is suspended according to a synchronized suspend command signal. Since the clock signal supply is suspended only while the integrated memory is in idling state, the power consumption of the system LSI can be saved without breaking down the integrated memory.

Memory controller for controlling an integrated memory undergoing logical state transitions

A television receiver comprising an information extracting circuit for extracting information from a format or content of an input video signal, a video signal processing circuit for processing this video signal by a program or data, a memory for storing the program and data, a CPU for controlling, operating or driving these elements, and a display device for displaying an image. The video signal processing circuit can, under the control of the CPU, decode the signal, correct or set the picture quality such as gradation and sharpness, or adaptively process an on-screen display based on the input video signal. The television receiver is also able to adaptively extend the functions of the television receiver corresponding to various signal formats.

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Takatsuki, Japan

Chikara Gotanda