Fujitsu Corporation

Nippon Telegraph and Telephone Public Corporation

Fujitu Limited

Chikai Ono

Kazuhiro Toyoda

Toshio Hayashi

Masao Suzuki

Kuniyasu Kawarada

Yoshinori Okajima

Hirokazu Yamazaki

Eiichi Nagai

Osamu Nomura

Michiyuki Hirata

Toru Fukui

Susumu Terawaki

According to an aspect of the present invention, a redundant file memory for recording first replacement information having an address of a defective cell to be replaced with a redundant cell is configured by a memory cell having the same configuration as an ordinary memory cell, and when accessing the ordinary memory cell, the redundant file memory can be accessed at the same time. Furthermore, second replacement information indicating whether or not the ordinary cell in correspondence with the stored address is a defective one is recorded in the redundant file memory. When accessing the ordinary memory cell, the first and second replacement information recorded in the redundant file memory are read out at the same time, and the defective cell is replaced with the redundant cell according to the replacement information.

Memory device having redundant cells

The present invention relates to a memory device, such as a FeRAM, of which redundancy structure is simplified. In the present invention, a redundancy file memory for recording a replacing information indicating the defective cell to be replaced into a redundancy cell is formed by a memory cell having the same structure as a normal memory cell, so that it is capable to access to a redundancy file memory at the same time when accessing to a normal memory cell. Then, the replacing information recorded in the redundancy file memory is concurrently read out when accessing to the normal memory cell, and the defective cell is replaced into a redundancy cell according to the replacing information.

Memory device having redundancy cells

A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.

Ferroelectric memory and method of testing the same

A level conversion circuit includes a level converter and a buffer gate circuit. A level converter includes two pairs of P-channel MOS transistors. A first input signal is supplied to one of the pair of P-channel MOS transistors and a second input signal is supplied to one of the other pair of P-channel MOS transistors. Each of the first and second input signals are complementary ECL-level signals. The buffer gate circuit includes two BiCMOS circuits. A first output signal from one of the pairs of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in one of the BiCMOS circuits. A second output signal from the other pair of P-channel MOS transistors is supplied to a gate of an N-channel MOS transistor provided in the other BiCMOS circuit. The first input signal is supplied directly to a gate of a P-channel MOS transistor provided in one the BiCMOS circuits. The second input signal is supplied directly to a gate of a P-channel MOS transistor provided in the other BiCMOS circuit. A first TTL-level output signal is output from one of the circuits, and a second TTL-level output signal is output from the other BiCMOS circuit.

Level conversion circuit for converting ECL-level signal into TTL-level

A bipolar type static memory cell comprising two cross connected circuits, each of the circuits including a transistor and a load element is disclosed. An N-type epitaxial layer, grown on an N.sup.+ -type buried layer, is used as a collector region of the transistor, and a P-type layer formed in the N-type epitaxial layer and an N.sup.+ -type layer formed in the P-type layer are used as a base region and an emitter region of the transistor. A P-type diffusion layer is formed in the N-type epitaxial layer from the surface of the epitaxial layer to reach and contact the buried layer. The structure results in the memory cell parasitic diodes being effectively eliminated from the cell together with the unwanted charge storage effects of the diodes.

Bipolar type static memory cell

A semiconductor device including a plurality of resistors. All the resistors are contained in circuit block regions which are arranged successively in a first direction. Each of the resistors is extended in the first direction. All of the resistors are set up in the form of a plurality of stages arranged in a second direction perpendicular to the first direction and in parallel with each other.

Semiconductor device

A semiconductor memory device included memory cells each including two PNPN cells cross-coupled with each other, the PNPN cells each including a load transistor and a multi-emitter transistor, the multi-emitter transistor comprising a read/write transistor and a data holding transistor. The read/write transistor has means for decreasing the current amplification factor of the read/write transistor when it operates inversely, whereby the operating speed of the device is improved.

Semiconductor memory device

An improvement of a semiconductor integrated circuit device of a memory cell array which is formed by integrated injection logic memory cells. The semiconductor integrated circuit includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions and which are formed by a semiconductor bulk. A current source is provided around the middle portion of each word line.

A semiconductor memory circuit device is disclosed. The semiconductor memory circuit device is conventionally comprised of a plurality of memory-cell arrays. Each of the memory-cell arrays is conventionally provided with a plurality of IIL memory cells, a pair of positive word line and negative work line and further a plurality of bit lines. In the semiconductor memory circuit device, at least one means for discharging electric charges is newly incorporated with each negative word line. Said means becomes active only when the corresponding memory-cell array changes from selection status to non-selection status.

I.sup.2 L Semiconductor memory circuit device

A semiconductor integrated circuit device of an I.sup.2 L type is disclosed. In this device, in order to clamp the potentials of bit lines at a desired level, a bit line clamp circuit comprising at least one dummy cell for which the fluctuation of characteristics induced by manufacturing processes are relative to those of the memory cells of an I.sup.2 L type is provided.

Semiconductor integrated circuit device

An improved semiconductor integrated circuit device having a memory cell array formed of integrated injection logic memory cells. The semiconductor integrated circuit according to the present invention includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions, one of the word lines being formed by a semiconductor bulk, current sources provided at least at both ends of the word lines or the bit lines.

An improved semiconductor integrated circuit device having an array of integrated injection logic memory cells arranged in matrix form, with word and bit lines connected to the memory cells arranged in lines. The second word line is formed by a semiconductor bulk, and dummy cells each comprising a shunt circuit for shunting the write current of the memory cells and a hold circuit for supplying a hold current to the memory cells are arranged in each line of the memory array.

A semiconductor integrated circuit device has an array of memory cells formed by integrated injection logic. A desired number of dummy cells are provided at both ends of each line of the array, so that a write current, which flows when the memory cell near the dummy cell is selected, is shunted by the dummy cell, thereby the currents which flow in the memory cells in the line of the memory array are equalized.

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Kawasaki, Japan

Chikai Ono