Kabushiki Kaisha Toshiba

Chikahiro Nakai

Hiroyuki Koinuma

A semiconductor memory device has one redundant memory cell block selection fuse circuit block for replacing a plurality of normal memory cell blocks with one or more redundant memory cell blocks. The number of the redundant memory cell block selection fuse circuit blocks is thereby reduced enough to restrain an increase in chip area. A lesser number of normal word lines than the number of normal word lines possessed by one normal memory cell block controlled by one normal decoder are set as a minimum replace unit, and a degree of replacing freedom can be improved.

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Yokohama, Japan

Chikahiro Nakai