Fujitsu Corporation

Chikahiro Deguchi

Yutaka Sekino

Hideyuki Negi

Hiroaki Watanabe

Shogo Shibazaki

Takeshi Nagase

Shinkichi Gama

Naoki Maezawa

Tomohiro Hayashi

Naoya Torii

Yoshiki Okumura

Souichi Okada

Yumi Fujiwara

A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.

Semiconductor integrated circuit and method of processing in semiconductor integrated circuit

A data receiving circuit includes a generating unit that generates multiple clocks with different phases from one another. The data receiving circuit includes multiple acquiring units that acquire data from a received data signal by using different clocks from one another out of the multiple clocks generated by the generating unit. The data receiving circuit includes a determining unit that determines whether the data acquired by the multiple acquiring units are consistent. The data receiving circuit includes a correcting unit that corrects the phases of the multiple clocks in a direction in which data inconsistency does not occur when the determining unit has determined that there is data inconsistent with the other data in the data acquired by the multiple acquiring units.

Data receiving circuit, information processing apparatus, a computer readable storage medium, and data receiving method

A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1&#x2266;k&#x2266;n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.

Memory test method and memory test device

A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful.

Configuration method and FPGA circuit re-executing configuration based on adjusted configuration data

A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.

Test apparatus, test method, and integrated circuit

An encryption circuit that reduces a scale of circuit and can achieve a certain level of high-speed processing in the implementation of the AES block cipher. A round processing unit comprises: a first Round Key Addition circuit that adds a round key value to input data; an intermediate register/Shift Row transformation circuit that temporarily stores the output of the first Round Key Addition circuit and executes Shift Row transformation; a Byte Sub transformation circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which executes Byte Sub transformation; a second Round Key Addition circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which adds round key values; a Mix Column transformation circuit that executes Mix Column transformation upon the outputs of the second Round Key Addition circuit; and a second selector that outputs to the second Round Key Addition circuit one of the outputs of a first selector, the intermediate register/Shift Row transformation circuit, the Byte Sub transformation circuit, and the Mix Column transformation circuit.

Encryption circuit

A method and apparatus for selecting test patterns of a plurality of groups of test patterns for testing parts of an integrated circuit. The plurality of groups of test patterns are applied to the parts of the integrated circuit to determine which parts are detected by the plurality of groups of test patterns. The detected parts form a group of parts. Each of the groups of test patterns is selectively identified as either necessary or unnecessary by repeatedly referring to the group of parts. Each time a respective group of test patterns is determined to be necessary, the group of parts is reduced by the parts detected by the respective group of test patterns determined to be necessary. After each of the groups of test patterns has been identified as either necessary or unnecessary, the unnecessary groups of test patterns are eliminated, to form a set of remaining necessary groups of test patterns for testing the integrated circuit.

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Kawasaki, Japan

Chikahiro Deguchi