Hitachi, Ltd.

Chikahiko Izumi

Kanji Kubo

Kenichi Wada

Shun Kawabe

Masahiro Hashimoto

Mamoru Hinai

Noriaki Hashimoto

Tsugio Momose

Kazuo Hibi

Humio Goto

Toshihiko Odaka

Riujiro Imai

A storage system includes a storage for storing data, and a store buffer for temporarily buffering data before storing it into the storage. A store request is applied to the store buffer, and store data accompanied by the store request is applied to the store buffer. When a fetch request for the storage does not exist, the store data buffered in the store buffer is transferred from the store buffer to the storage and is stored therein.

Storage system using comparison and merger of encached data and update

This storage system is designed to refer to a translation lookaside buffer, a buffer address array and a buffer storage in parallel. The translation lookaside buffer translates a logical address requesting memory access into a real address. The buffer storage retains part of the data retained in blocks by main storage and outputs data from M blocks in accordance with the logical address to M aligners. The buffer address array retains the addresses in MS of the data stored in each of the blocks in the buffer storage, and outputs M addresses in accordance with the logical address. A comparator compares the real addresses from the translation lookaside buffer with the addresses from the buffer address array, selects one of the outputs from the aligners, and transfers that output to a processor.

Storage system having buffer storage

In a data processing system having an instruction buffer, inconsistency between an instruction stored in a main memory and the same instruction present in the instruction buffer occurs at the time of a store operation to the memory if the instruction supplied to the store area of the main memory previously has been prefetched to and is present in the instruction buffer. The changing in the memory of the content of the instruction prefetched to the instruction buffer and the fact that the changed instruction is about to be executed are detected on the basis of the instruction fetch address of an instruction to be fetched from the memory to the instruction buffer, the instruction address of the next instruction to be executed, information concerning the byte position at which the instruction to be executed is stored, the store address at which the changed instruction is stored in the main storage and information concerning the byte position in the main storage of the instruction which is changed by the store operation. When the execution of the instructions proceeds to the changed instruction, the content of the instruction buffer is invalidated.

Apparatus for invalidating the content of an instruction buffer by

A data shunting and recovering device is provided to shunt and hold the data stored in a register and its address before writing the register during a delay period following generation of an interrupt. This data is then restored into the register when an instruction of recovering is given. Therefore, it is allowed to achieve the moderating effects of delaying the stopping of the stage advance in data processing upon generation of an instruction for interruption without loss of data stored in the memory prior to writing during this delay period.

Data shunting and recovering device

A data processing apparatus incorporating a function referred to as the scan-out diagnosis function for reading out and checking sequentially internal states of the apparatus. In addition to the address designating means for the scan-out diagnosis function, an address register is provided which is validated in place of the address designating means only when the latter is inoperative, to thereby designate a particular flip-flop. An observing means is provided for observing continuously the state of the particular flip-flop as read out. Thus, the state of the flip-flop designated by the address register can be continually visually observed independently of the address designating means for the scan-out diagnosis function.

Data processing apparatus having diagnosis function

A multiple virtual storage control system for a data processing system for handling a plurality of virtual spaces is disclosed. Virtual addresses indicative of addresses in the virtual spaces are translated to real addresses by a translation table. When a new virtual space is established by setting a first address or segment table origin address (STO address) of the translation table, a virtual space number is assigned to the established virtual space by an STO address stack, which comprises a definite number of registers. The number of virtual space numbers assigned is larger than the number of registers. The virtual addresses and the corresponding real addresses are stored in a high-speed address translator so that the virtual addresses are translated to the real addresses at a high speed. When an overflow of the virtual space number assigned in the STO address stack takes place, the plurality of virtual spaces registered in the high-speed address translator are simultaneously purged.

Multiple virtual storage control system

A general purpose data processing apparatus is provided which is adapted also for processing vector instructions. An instruction control unit reads instructions out of a memory and decodes them. If the instructions are different from vector instructions, an arithmetic unit performs the instructed operations. If the instructions are vector instructions, the subsequent control is performed by a vector instruction control unit. The vector instruction control unit decodes the vector instructions and controls the vector operands to cause the same arithmetic unit to perform the vector operation in accordance with the vector operands. Thus, the general purpose data processing apparatus can process vector instructions at high speed.

General purpose data processing apparatus for processing vector

In a data processing system in which a single main memory is shared by two or more basic processing units, each unit is provided with a first buffer address array which stores the addresses of data stored in the associated buffer memory and is searched by this processing unit and with second buffer address arrays which store the copy of the content of the first buffer address array and are searched by the store addresses from the other processing units, so that the information stored in the buffer memory of one processing unit may be prevented from becoming different from the information stored in the main memory when another processing unit performs a storing operation, without degrading the processing efficiency of the system.

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Hadano, Japan

Chikahiko Izumi