Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Other

Chikaaki Kodama

Toshiya Kotani

Hiromitsu Mashita

Fumiharu Nakajima

Kosuke Yanagidaira

Takafumi Taguchi

Ryota Aburada

Shigeki Nojima

Kazuyuki Masukawa

Hirotaka Ichikawa

Yuko Kono

Yasunobu Kai

Seiro Miyoshi

Takaki Hashimoto

Tetsuaki Matsunawa

Koichi Nakayama

Taiki Kimura

Shoji Mimotogi

Mikihiko Ito

Kazuhito Kobayashi

Akiko Mimotogi

Taiga Uno

Hidefumi Mukai

Yuji Setta

Katsumi Iyanagi

Keishi Sakanushi

Yoko Yokoyama

Motohiro Okada

Michiya Takimoto

Katsuyoshi Kodera

Nozomu Furuta

Shunsuke Kagaya

Shuhei Sota

Hiromitusu Mashita

Satomi Nakamura

Takanori Urakami

A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Manufacturing method of a semiconductor device and method for creating a layout thereof

In an assist pattern arrangement method according to an embodiment, a plurality of patterns, in which an assist pattern is to be arranged, are extracted from a design pattern that is prepared in advance. Then, a resolution map of the extracted pattern is calculated. The resolution map includes a first pattern that increases a resolution of the pattern and a second pattern that decreases the resolution of the pattern. After the resolution map is calculated, a plurality of calculated resolution maps are added. Then, the assist pattern is arranged on the design pattern on the basis of the addition result.

Assist pattern arrangement method and recording medium

According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)second sidewall film matching a pattern of a n(where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2)&#xd7;(&#x3bb;/NA) or less when an exposure wavelength of an exposure device is &#x3bb;, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.

Microstructure device and method for manufacturing the same

According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.

Pattern data generation method, pattern verification method, and optical image calculation method

A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

Method of fabricating semiconductor device and semiconductor device

Growing community of inventors

Yokohama, Japan

Chikaaki Kodama