Hong Kong Applied Science and Technology Research Institute Company, Limited

Chik Wai David Ng

Kwok Kuen David Kwong

Yat To William Wong

Ho Ming Karen Wan

Kam Chuen Wan

Hing Kit Kwan

Wai Kit Victor So

A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.

Single-power-transistor battery-charging circuit using voltage-boosted clock

An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.

ESD protection using a capacitivly-coupled clamp for protecting low-voltage core transistors from high-voltage outputs

An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.

Slew-rate-enhanced error amp with adaptive transconductance and single dominant pole shared by main and auxiliary amps

A bandgap reference voltage generator has a first stage that generates a first current that is complementary-to-absolute-temperature (Ictat) and a second stage that generates a current that is proportional-to-absolute-temperature (Iptat). The Ictat and Iptat currents are both forced through a summing resistor to generate a voltage that is relatively independent of temperature, since the Ictat and Iptat currents cancel out each other's temperature dependencies. A PMOS output transistor drives current to an output load to maintain the load at the reference voltage. An op amp drives the gate of the PMOS output transistor and has inputs connected to emitters of PNP transistors in the second stage. A series of resistors generate the reference voltage between the PMOS output transistor and ground and drives bases of the PNP transistors and includes the summing resistor. Parasitic PNP transistors in an all-CMOS process are used. The generator operates with a 1-volt power supply.

Low voltage high-output-driving CMOS voltage reference with temperature compensation

An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.

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Hong Kong, China

Chik Wai David Ng