The Hong Kong University of Science and Technology

Chik Patrick Yue

Kei May Lau

Li Ping Wang

Johnny Kin On Sin

Zhaojun Liu

Quan Pan

A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the &#xbc;-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLF(s). The VLF(s) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a &#x2212;3-dB corner frequency of 40 MHz.

PAM-4 receiver with jitter compensation clock and data recovery

The present disclosure provides adaptive cascaded equalization circuits for frequency spectrum compensation. The cascaded equalization are formed in circuit configurations to achieve configurable roll-up frequency responses to compensate for the loss of signal channels in the wire-line or optical communications, particularly but not exclusively, for the loss of signal trace in the wire-line communications, and photodetectors used in the optical communications. These cascaded equalization circuits include two or more stages of equalizers. The peaking frequencies of each stage are set to be different from each other, so that the overall frequency response characteristic has a unique frequency response with a roll-up slope. The equalization function is automatically tuned by an adaptive feedback control loop.

Adaptive cascaded equalization circuits with configurable roll-up frequency response for spectrum compensation

A lighting device is provided. The lighting device includes a substrate, integrated circuits (), embedded passive components (), and a lighting component (), the device being arranged in an architecture having three layers: an integrated circuits layer () including the integrated circuits (), wherein the integrated circuits layer () is integrated on a first side of the substrate; an embedded passive components layer () including the embedded passive components (), wherein the embedded passive components () are embedded in grooves formed in the substrate and wherein the embedded passive components are connected to the integrated circuits () through vias () in the substrate; and a bonded layer (), including the lighting component (), the lighting component () being connected to the integrated circuit layer () through flip-chip bonding or monolithic integration.

Power system-on-chip architecture

Image projection utilizing light-emitting diodes on a silicon (LEDoS) substrate is described herein. LEDoS devices selectively activate LED pixels to produce light. Light can excite color conversion materials of the LEDoS devices to form color images. Images can be projected onto a projection surface.

Growing community of inventors

Hong Kong, China

Chik Patrick Yue