Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Chii-Ming M Wu

Hsing-Lien Lin

Hai-Dang Trinh

Chih-Wei Chang

Fa-Shen Jiang

Shau-Lin Shue

Mei-Yun Wang

Chun Hsiung Tsai

Cheng-Ta Wu

Tzu-Chung Tsai

Cheng-Yuan Tsai

Ming-Huan Tsai

Yu-Lien Huang

Chung-Yi Yu

Sen-Hong Syue

Rei-Lin Chu

Ziwei Fang

Chun-Feng Nieh

Wei-Jung Lin

Cheng-Tung Lin

Fang-Cheng Chen

Cheng-Po Chau

Kun-Tzu Lin

Wen-Chi Tsai

Chen-Tung Lin

Lan-Fang Chang

Chia-Shiung Tsai

Shiu-Ko JangJian

Ping-Wei Wang

Yao-Wen Chang

Han-Ting Tsai

Da-Wen Lin

Yimin Huang

Chun-Fai Cheng

Chiang-Ming Chuang

Wei-Han Fan

Yu Lien Huang

Yeur-Luen Tu

Chi-Cherng Jeng

Ming-Hsing Tsai

Ru-Shang Hsiao

Tsan-Chun Wang

Fu-Ting Sung

Shing-Chyang Pan

Ming-Ta Lei

Yi-Huan Chen

Chia-Hua Lin

Chao-Hsien Peng

Bi-Shen Lee

Ju-Wang Hsu

Yan-Ming Tsai

Chia-Han Lai

Huang-Ming Chen

Eugene I-Chun Chen

Shih-Wei Chou

Chun-Han Tsao

Hung-Chang Hsu

Yung-Chung Chen

Chun-Wen Nieh

Cheng-Te Lee

Edwin Liou

Ching Ju Yang

Chung-Wen Wang

Chiang-Sheng Chin

Chaing-Ming Chuang

Gin Jei Wang

Jhon-Jhy Liaw

Ching-Hua Hsieh

Shih-Chieh Chang

Hun-Jan Tao

Tsz-Mei Kwok

Pang-Yen Tsai

Su-Hao Liu

Chung-Long Chang

Chien-Chang Su

Chun-Yi Lee

Chu-Yun Fu

Yuan-Hung Chiu

Huai-Ying Huang

Hsien-Hsin Lin

Yi-Fang Pai

Chin-I Liao

Chien-Wei Lee

Chen-Chieh Chiang

Chen Cheng Chou

Chung-Ren Sun

Wei-Barn Chen

Ting-Huang Kuo

Chih-Chien Chang

Shiu-Ko Jangjian

Wesley Lin

Tzu Kai Lin

Chia Ping Lo

Mao-Rong Yeh

Shyn-Ren Chen

Wan-Yih Lien

Chun-Ju Huang

Shiun-Huan Lai

Hung Pin Chen

Julie Yang

A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.

Physical vapor deposition chamber with target surface morphology monitor

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode structure disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. The bottom electrode structure has an upper surface including a noble metal. A diffusion barrier layer is over the bottom electrode structure, a data storage structure is over the diffusion barrier layer, and a top electrode structure is over the data storage structure. The diffusion barrier layer is configured to mitigate a diffusion of noble metal atoms from the bottom electrode structure to the data storage structure.

RRAM structure

Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Method to reduce breakdown failure in a MIM capacitor

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A dielectric layer is formed on the bottom electrode. A first top electrode layer is deposited on the dielectric layer by a first deposition process. A diffusion barrier layer is deposited on the first top electrode layer by a second deposition process different from the first deposition process. A second top electrode layer is deposited on the diffusion barrier layer by a third deposition. The third deposition process is the same as the first deposition process.

Diffusion barrier layer in top electrode to increase break down voltage

Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Resistive memory cell having a low forming voltage

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

MIM capacitor with a symmetrical capacitor insulator structure

A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

Semiconductor device and method for manufacturing the same

A method for forming a semiconductor memory structure include forming a pillar structure. The pillar structure includes a first conductive layer, a second conductive layer and a data storage material layer between the first and second conducive layers. A sidewall of the first conductive layer, a sidewall of the data storage layer and a sidewall of the second conductive layer are exposed. An oxygen-containing plasma treatment is performed on the pillar structure to form hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer. An encapsulation layer is formed over the pillar structure and the dielectric layer. The encapsulation layer is in contact with the hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer.

Method for forming semiconductor structure

Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

Top-electrode barrier layer for RRAM

Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.

Data storage structure for improving memory cell reliability

A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

Strained gate semiconductor device having an interlayer dielectric doped with large species material

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.

Rram structure

A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.

Method for forming semiconductor device having isolation structures with different thicknesses

A method for manufacturing reflective structure is provided. The method includes the operations as follows. A metallization structure is received. A plurality of conductive pads are formed over the metallization structure. A plurality of dielectric stacks are formed over the conductive pads, respectively, wherein the thicknesses of the dielectric stacks are different. The dielectric stacks are isolated by forming a plurality of trenches over a plurality of intervals between each two adjacent dielectric stacks.

Method for manufacturing reflective structure

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.

Growing community of inventors

Hsinchu, Taiwan

Chii-Ming M Wu