Taiwan Semiconductor Manufacturing Comp. Ltd.

Chii-Horng Li

Tze-Liang Lee

Yen-Ru Lee

Hsueh-Chang Sung

Tsz-Mei Kwok

Kun-Mu Li

Chien-I Kuo

Heng-Wen Ting

Li-Li Su

Ming-Hua Yu

Pei-Ren Jeng

Yee-Chia Yeo

Lilly Su

Jung-Chi Tai

Tzu-Ching Lin

Chien-Chang Su

Yu-Hung Cheng

Chih-Yun Chin

Pang-Yen Tsai

Yi-Hung Lin

Syun-Ming Jang Jang

Chao-Cheng Chen

Kei-Wei Chen

Yi-Fang Pai

Chien-Wei Lee

Yan-Ting Lin

Roger Tai

Ying-Wei Li

Tzu-Hsiang Hsu

Wei Hao Lu

Cheng-Hsiung Yen

Jung-Jen Chen

Wei Te Chiang

Harry Chuang

Jr-Hung Li

Chien-Liang Chen

Jeng-Wei Yu

Tsung-Hsi Yang

Shih-Hao Lo

Che-Hui Lee

Wen-Chih Yang

Eric Peng

Yih-Ann Lin

Chih-Shan Chen

Ta-Chun Ma

Ying Hao Hsieh

Davie Liu

Yang-Tai Hsiao

Wei-Yang Lee

Ziwei Fang

Yi-Jing Lee

Tsan-Chun Wang

Ji-Yin Tsai

Chia-Ao Chang

Jhi-Cherng Lu

Chang-Shen Lu

Feng-Cheng Yang

Chih-Chiang Chang

Chien-Hao Chen

Kuo-Tai Huang

Jin-Aun Ng

Ting-Yeh Chen

Hao-Ming Lien

Chia-Ling Chan

Cheng-Po Chau

Jun-Lin Yeh

Kang-Cheng Lin

Che-Yu Lin

Meng-Ku Chen

Wei-Min Liu

Chun-An Lin

Tuoh Bin Ng

Cheng-Wen Cheng

Chung-Hau Fei

Chih-Hung Nien

Cheng-Yen Wen

Shao-Fu Fu

Chun Ming Lin

Jui-Hsuan Chen

Harry-Hak-Lay Chuang

Mong-Song Liang

Bao-Ru Young

Ming Zhu

Chien-Hung Chen

Chia-Pin Lin

Wei-Yuan Lu

Jyh-Huei Chen

De-Wei Yu

Feng-Ching Chu

Bo-Yu Lai

Chien-Chih Lin

Chun-Hung Huang

Bing-Hung Chen

Li-Wei Chou

Mong Song Liang

Pin-Ju Liang

Yi-Cheng Li

Sin-Hua Wu

Wei-Hao Lu

Ssu-Yi Li

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

FETS and methods of forming FETS

A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.

Nano-structure transistors with air inner spacers and methods forming same

A semiconductor device including a seeding layer in the source/drain region and a method of forming is provided. The semiconductor device may include a plurality of nanostructures over a substrate, a gate structure wrapping around the plurality of nanostructures, a source/drain region adjacent the plurality of nanostructures, and inner spacers between the source/drain region and the gate structure. The source/drain region may include a polycrystalline seeding layer covering sidewalls of the plurality of nanostructures and sidewalls of the inner spacers, and a semiconductor layer over the seeding layer. The semiconductor layer may have a higher dopant concentration than the seeding layer.

Semiconductor device and method

A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.

Source/drain regions of semiconductor device and method of forming the same

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.

Source/drain structure for semiconductor device

Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a multilayer source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a source/drain barrier material is deposited using a bottom-up deposition process at the bottom of the opening to a level below the multilayer stack. A multilayer source/drain region is formed over the source/drain barrier material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the multilayer source/drain region being electrically coupled to the stack of nanostructures.

Semiconductor devices with a source/drain barrier layer and methods of manufacture

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

Epitaxial source/drain recess formation with metal-comprising masking layers and structures resulting therefrom

A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Low Ge isolated epitaxial layer growth over nano-sheet architecture design for RP reduction

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

FETs and methods of forming FETs

A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

Fin field-effect transistor device and method of forming

A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.

System and methods of manufacturing semiconductor devices

A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Method for forming an undoped region under a source/drain

A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Epitaxy regions with large landing areas for contact plugs

A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

Semiconductor device and method of manufacture

Growing community of inventors

Zhubei, Taiwan

Chii-Horng Li