Mediatek Singapore Pte. Ltd.

Mediatek Corporation

Accton Technology Corporation

Chii-Horng Chen

Shih-Chi Shen

Chun-Ming Kuo

Wen-Chang Lee

Xiaochuan Guo

Yen-Chen Chen

Fei Xu

Augusto Marques

Yabo Li

Mingjun Xu

Yaochao Liu

Biwei Chen

Chong-Yung Chi

Ai-Hsuan Liu

An embodiment of the invention provides a communication apparatus comprising a radio transceiver and a modem processor. The radio transceiver is configured to transmit or receive wireless signals in a wireless network. The modem processor is coupled to the radio transceiver and configured to perform operations comprising: dividing a tracking reference signal (TRS) set into a plurality of TRS subsets; scheduling a first part of the plurality of TRS subsets for a beam management; and scheduling a second part of the plurality of TRS subsets for a synchronization.

Communication apparatus and method for handling a tracking reference signal scheduling

A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock. The loop bandwidth controller checks at least one indicator indicative of injection pulling/pushing of the PLL to configure a loop bandwidth of the PLL. In one exemplary design, the loop bandwidth controller sets the loop bandwidth of the PLL by controlling a configuration of a loop filter included in the PLL. For example, the PLL is an all-digital phase-locked loop (ADPLL), and the loop filter is a digital loop filter of the ADPLL.

Frequency synthesizer with injection pulling/pushing suppression/mitigation and related frequency synthesizing method thereof

A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Frequency synthesizer and related method for improving power efficiency

A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

Method and apparatus for measuring/compensating mismatches in digitally-controlled oscillator

A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

Clock generating apparatus and frequency calibrating method of the clock generating apparatus

A blind adaptive filtering method for receivers of communication systems without need of training sequences, and whose performance is close to that of the non-blind linear minimum mean square error (LMMSE) receivers with training sequences required in practical environments of finite signal-to-noise (SNR) and data length. This algorithm is an iterative batch processing algorithm using cumulant based inverse filter criteria with super-exponential convergence rate and low computational load. The receivers to which the presented algorithm can be applied are (but not limited to) equalizers of conventional time division multiple access (TDMA) digital communication systems, and smart antennas based on space-time processing for wireless communication systems.

Growing community of inventors

Hsinchu County, Taiwan

Chii-Horng Chen