Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Chihoko Shigeta

Kazuya Kitsunai

Yoshihisa Kojima

Hiroyuki Nemoto

Hiroyuki Aizu

Noriya Sakamoto

Michihiro Fukushima

According to one embodiment, a memory system includes a first and second nonvolatile memory each including a plurality of memory cells; and a memory controller configured to perform, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory. The memory controller is configured to change a setting of at least one unperformed write process among the first set and second set of write processes based on differences in progress between the first set and second set of write processes, the first set and second set of write processes being performed in parallel.

Memory system and controlling method of memory system

According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.

Memory system and control method

A storage device includes a non-volatile memory and a control circuit that reads data in units of cluster, and erase data in units of logical block which includes a plurality of clusters. Data in each cluster includes a first error correction code and each cluster is arranged in at least one error correction group, each including clusters and a second error correction code. The control circuit performs a refresh operation in units of cluster such that refresh target data in a cluster of a first logical block is moved to a cluster of a second logical block. A first error correction group related to the refresh target data includes the cluster of the first logical block before the moving, and the first error correction group related to the refresh target data includes a cluster of the first logical block and a cluster of the second logical block after the moving.

Storage device and error correction method for storage device

In at least one embodiment, a reception apparatus includes a discrimination data receiver configured to receive discrimination data that is transmitted from outside the reception apparatus and that has been associated with display information to be displayed; and an output controller configured to control output of the display information to two or more display screens according to the discrimination data.

Growing community of inventors

Kunitachi, Japan

Chihoko Shigeta